F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

6.1. Ethernet to CPRI Design Example: Functional Description

This sectio suppots the followig cofiguatios:
Table 21.  Suppoted Desig Example Vaiats fo Etheet to CPRI Potocol Desig Example
Base Vaiat (Statup IP/Mode) Dyamic Recofiguatio Vaiats
25G with RS-FEC 25G-1 Etheet with RS-FEC
10G-1 Etheet
24G CPRI with RS-FEC
10G CPRI
9.8G CPRI
4.9G CPRI
2.4G CPRI
25G-1 with RS-FEC (with 1GE) 25G-1 Etheet with RS-FEC
10G-1 Etheet
1G-1 Etheet
24G CPRI with RS-FEC
10G CPRI
9.8G CPRI
4.9G CPRI
2.4G CPRI
25G-1 PTP with RS-FEC (with 1GE PTP) 25G-1 with RS-FEC ad PTP
10G-1 with PTP
1G-1 with PTP
24G CPRI with RS-FEC
10G CPRI
9.8G CPRI
4.9G CPRI
2.4G CPRI
Note: The Etheet to CPRI Potocol Desig Example demostates a total of 8 Dyamic Recofiguatio vaiats. Howeve, coceptually, you ca also pefom dyamic ecofiguatio switchig betwee Etheet mode to ay othe F-Tile CPRI PHY Itel FPGA IP coe suppoted mode that ae ot listed i the table (fo example, 12G CPRI RS-FEC o 6G CPRI).

Sectio Cotet
Etheet to CPRI Dyamic Recofiguatio Desig Example: Simulatio Testbech
Etheet to CPRI Dyamic Recofiguatio Hadwae Desig Example
Etheet to CPRI Dyamic Recofiguatio Desig Example: Reset Scheme

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