F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

4.1.1.2. Theory of Operation

The F-Tile Auto-Negotiatio ad Lik Taiig fo Etheet Itel® FPGA IP icludes a pe-pot wie amed pot_state, which sigals to the Use Logic block that the auto-egotiatio (AN) pocess is complete ad the esults ae eady to be accessed. This sigal coespods to bit[0] of the Use_logic_cotol_i pot.
  • Pot State Sigal:
    • Pot_state idicates AN pocess completio.
    • Coespods to bit[0] of Use_logic_cotol_i pot.
  • Whe pot_state is asseted ad AN/LT IP is i PAUSE:
    • The Use Logic block assets elevat esets to the F-Tile Etheet Multiate Itel® FPGA IP .
    • The Use Logic block waits fo the coespodig eset ackowledgmets.
  • Whe AN/LT is paused:
    • The Use Logic block tigges the appopiate dyamic ecofiguatio flow based o the mode selected via a local paamete i the top-level of the example desig, passed ito the Use_logic_cotol_i pot.
    • The F-Tile Dyamic Recofiguatio Suite Itel® FPGA IP ad F-Tile Etheet Multiate Itel® FPGA IP exclusively hadle dyamic ecofiguatio.
    • The F-Tile Auto-Negotiatio ad Lik Taiig fo Etheet Itel® FPGA IP does ot pefom ay dyamic ecofiguatio opeatios.
  • Oce dyamic ecofiguatio is complete:
    • The Use Logic block pogams the seq_foce_mode egiste i the F-Tile Auto-Negotiatio ad Lik Taiig fo Etheet Itel® FPGA IP with the iteded data mode ate, if ecessay.
    • The Use Logic block upauses the F-Tile Auto-Negotiatio ad Lik Taiig fo Etheet Itel® FPGA IP
    • The F-Tile Auto-Negotiatio ad Lik Taiig fo Etheet Itel® FPGA IP completes the Lik Taiig ad moves to data mode.
  • Post-ecofiguatio actios:
    • The Use Logic block pefoms the equied wites ito the F-Tile Etheet Multiate Itel® FPGA IP soft CSRs.
    • The Use Logic block de-assets esets to the F-Tile Etheet Multiate Itel® FPGA IP .
I the followig Auto-Negotiatio ad Lik Taiig (AN/LT) + Dyamic Recofiguatio (DR) flow diagam, the blocks eclosed i blue epeset the pocesses executed by the Use Logic block.
Figue 23. AN/LT + DR Flow
Level Two Title