F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example

Figue 40. Etheet to CPRI Dyamic Recofiguatio Hadwae Desig Example Block Diagam (25GE-1 with RS-FEC Base Vaiat)
Figue 41. Etheet to CPRI Dyamic Recofiguatio Hadwae Desig Example Block Diagam (25GE-1 with RS-FEC[with 1GE])
Figue 42. Etheet to CPRI Dyamic Recofiguatio Hadwae Desig Example Block Diagam (25G-1 PTP with RS-FEC (with 1G PTP)

I the hadwae desig example, the ISSP modules cotol the DUT IP eset sigals, d_mode selectio ad shows the status sigals. The hadwae test scipts ope sevice to the ISSP to ead ad dive the values. A JTAG maste is istatiated to access the Avalo® memoy-mapped itefaces. By default, the iteal seial loopback mode is disabled. The desig equies a exteal loopback module to u the default hadwae test scipt. You ca eable the iteal seial loopback by settig the loopback_mode paamete to 1 i the paamete.tcl file.

The hadwae desig example executes the dyamic ecofiguatio tasitio pocess based o use selectio as stated i sc/paamete.tcl file ad checks the DUT IP status, clea the MAC statistics befoe sedig 16 packets, ad lastly display the MAC statistics. Thee is a default dyamic ecofiguatio tasitio sequece, but use ca always modify the DR_TRANSITION aay vaiable i sc/paamete.tcl file.

DR_TRANSITION: Iteded DR sequece aay, size of this aay vaiable detemies the umbe of dyamic ecofiguatio to be pefomed. Fo example, if you wat to achieve the followig dyamic ecofiguatio sequece fo 25G-1 Base Vaiat: Etheet 25G-1 > CPRI 24G with RSFEC > Etheet 10G-1, the vaiables chages ae: 
set DR_TRANSITION(0)"24G_RSFEC"
set DR_TRANSITION(1) "1x10GE"

Hadwae Flow fo Desig Example:

The hadwae test desig <desig_example_di>/hadwae_test_desig/ diectoy cotais a hwtest subdiectoy that cotais .tcl scipt fo dyamic ecofiguatio hadwae testig. Follow the steps show below to test the desig example i hadwae.
Figue 43. Hadwae Flow fo Etheet to CPRI Dyamic Recofiguatio Hadwae Desig Example

A successful u displays Test <ftile_etheet_cpi_d_test> Passed i the System Cosole widow.

Fo moe ifomatio to test the desig example i hadwae, efe to Testig the Hadwae Desig Example.

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