F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

2.1.1. CPRI Multirate Design Example: Simulation Testbench

Figue 7. Simulatio Testbech Block Diagam

The testbech pogam is cotollig the testbech compoets via Avalo® memoy-mapped iteface access, status ad cotol sigals. The Avalo® memoy-mapped iteface abite is used to decode the Avalo® memoy-mapped iteface access fom testbech pogam ito multiple Avalo® memoy-mapped iteface slaves.

Simulatio Flow fo Desig Example:
  1. Disable the Testbech packet oud-tip measuemet.
  2. Powe up the CPRI PHY Multiate IP DUT based o pofile 0 (24G RS-FEC).
  3. Iitialize the testbech vaiables based o powe-up pofile. The vaiables ae:
    • cpi_speed: To idicate the speed of the cuet pofile.
    • eable_sfec: To idicate whethe RS-FEC is eabled o disabled fo the cuet pofile.
    • cuet_d_pofile: To idicate the ID of the cuet pofile.
  4. Pefom dyamic ecofiguatio.
  5. Check the testbech eo flag ad detemie whethe testbech passed o failed. This eo flag is set to 1 if thee is ay eo afte dyamic ecofiguatio taffic tests.
Fo customizatio, you ca modify the DR_NUM ad DR_SEQ localpaam to cofigue test flow. Pofile ID is passed ito Dyamic Recofiguatio IP to cofigue the iteded dyamic ecofiguatio task.
  • DR_NUM: Numbe of Dyamic Recofiguatio tasitio
  • DR_SEQ: Dyamic Recofiguatio sequece
Fo example, you wat to achieve this Dyamic Recofiguatio sequece: 24G RS-FEC > 10G > 4.9G. The localpaams chages ae:
  • DR_NUM = 2
  • DR_SEQ = {DR_TO_4P9G, DR_TO_10G};
Default cofiguatio fo the desig example: 
localpaam DR_TO_24G_RSFEC   = 4'h0;
localpaam DR_TO_24G         = 4'h1;
localpaam DR_TO_12G_RSFEC   = 4'h2;
localpaam DR_TO_12G         = 4'h3;
localpaam DR_TO_10G_RSFEC   = 4'h4;
localpaam DR_TO_10G         = 4'h5;
localpaam DR_TO_9P8G        = 4'h6;
localpaam DR_TO_6G          = 4'h7;
localpaam DR_TO_4P9G        = 4'h8;
localpaam DR_TO_3G          = 4'h9;
localpaam DR_TO_2P4G        = 4'ha;
localpaam DR_TO_1G          = 4'hb;

localpaam DR_NUM = 5;
localpaam [3:0] DR_SEQ [DR_NUM-1 : 0] = {DR_TO_24G_RSFEC, DR_TO_2P4G, DR_TO_4P9G, DR_TO_9P8G, DR_TO_10G};
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