F-Tile Dynamic Reconfiguration Design Example User Guide
Visible to Intel only — GUID: dmq1634754093053
Ixiasoft
Visible to Intel only — GUID: dmq1634754093053
Ixiasoft
2.1.1. CPRI Multirate Design Example: Simulation Testbench
The testbench program is controlling the testbench components via Avalon® memory-mapped interface access, status and control signals. The Avalon® memory-mapped interface arbiter is used to decode the Avalon® memory-mapped interface access from testbench program into multiple Avalon® memory-mapped interface slaves.
- Disable the Testbench packet round-trip measurement.
- Power up the CPRI PHY Multirate IP DUT based on profile 0 (24G RS-FEC).
- Initialize the testbench variables based on power-up profile. The variables are:
- cpri_speed: To indicate the speed of the current profile.
- enable_rsfec: To indicate whether RS-FEC is enabled or disabled for the current profile.
- current_dr_profile: To indicate the ID of the current profile.
- Perform dynamic reconfiguration.
- Check the testbench error flag and determine whether testbench passed or failed. This error flag is set to 1 if there is any error after dynamic reconfiguration traffic tests.
- DR_NUM: Number of Dynamic Reconfiguration transition
- DR_SEQ: Dynamic Reconfiguration sequence
- DR_NUM = 2
- DR_SEQ = {DR_TO_4P9G, DR_TO_10G};
localparam DR_TO_24G_RSFEC = 4'h0; localparam DR_TO_24G = 4'h1; localparam DR_TO_12G_RSFEC = 4'h2; localparam DR_TO_12G = 4'h3; localparam DR_TO_10G_RSFEC = 4'h4; localparam DR_TO_10G = 4'h5; localparam DR_TO_9P8G = 4'h6; localparam DR_TO_6G = 4'h7; localparam DR_TO_4P9G = 4'h8; localparam DR_TO_3G = 4'h9; localparam DR_TO_2P4G = 4'ha; localparam DR_TO_1G = 4'hb; localparam DR_NUM = 5; localparam [3:0] DR_SEQ [DR_NUM-1 : 0] = {DR_TO_24G_RSFEC, DR_TO_2P4G, DR_TO_4P9G, DR_TO_9P8G, DR_TO_10G};