2.1.2. CPRI Multirate Hardware Design Example
Figue 8. CPRI Multiate Hadwae Desig Example Block Diagam
I the hadwae desig example, the eset, status, ad cotol sigals fom packet cliets, F-Tile CPRI PHY Multiate Itel® FPGA IP, ad F-Tile Dyamic Recofiguatio Suite Itel® FPGA IP i the example desig ae coected to I-System Souces ad Pobes IPs (ISSP). The hadwae test scipts ope sevice to the ISSP to ead ad dive the values. A JTAG host is istatiated to access the Avalo® memoy-mapped itefaces.
Hadwae Flow fo Desig Example:
- Eable the packet oud-tip measuemet.
- Pefom the detemiistic latecy test flow.
- Pit the detemiistic latecy data to det_latecy.log file.
- Powe up the CPRI PHY Multiate IP DUT based o pofile 0 (24G RSFEC).
- Iitialize the testbech vaiables based o powe-up pofile. The vaiables ae:
- cpi_speed: To idicate the speed of the cuet pofile.
- eable_sfec: To idicate whethe RS-FEC is eabled o disabled fo the cuet pofile.
- cuet_d_pofile: To idicate the ID of the cuet pofile.
- Pefom dyamic ecofiguatio.
- Check the testbech eo flag ad detemie whethe testbech passed o failed. This eo flag is set to 1 if thee is ay eo afte dyamic ecofiguatio taffic tests.
Fo customizatio, you ca modify the DR_TRANSITION aay vaiable i sc o paamete file to cofigue test flow. Pofile ID is passed ito Dyamic Recofiguatio IP to cofigue the iteded dyamic ecofiguatio task.
- DR_TRANSITION: Iteded dyamic ecofiguatio sequece aay. The size of this aay vaiable detemies the umbe of dyamic ecofiguatio to be pefomed.
set DR_TRANSITION(0) "10G" set DR_TRANSITION(1) " 4P9G"
The sample output fo the CPRI Multiate hadwae desig example is show below.
Sample output fo CPRI Multiate hadwae desig example:
Ifo: Numbe of Chaels = 1 Ifo: JTAG Pot ID = 1 Ifo: Powe Up Vaiat = 24G_RSFEC Ifo: Stat of ftile_d_cpi_test Ifo: Basic CPRI DR test INFO: Checkig PLL lock status... iopll_sclk_locked 1 INFO: IOPLL sclk is locked INFO: Set Recofig Reset INFO: Release Recofig Reset Loop 0 INFO: Set RT Coute INFO: Chael 0: Set TX Reset INFO: Chael 0 : Checkig tx eset ack status... INFO: TX fully i eset state INFO: Chael 0: Set RX Reset INFO: Chael 0 : Checkig x eset ack status... INFO: RX fully i eset state Ifo: Chael: 0 Cofiguig ED to CPRI 10G .... Ifo: Wait fo DR Ready.... Ifo: Tigge DR iteupt Ifo: Wait fo DR iteupt Ack.... Ifo: DR Request ackowledged Ifo: Wait fo DR Cofig to be doe.... Ifo: DONE Recofigue to 10G. INFO: Chael 0: Cofiguig cpi_speed Ifo: Chael: 0 Loop: 0 De-assetig eset to CPRI 10G .... INFO: Chael 0: Release TX Reset Ifo: Check TX Ready Attempt: 1 INFO: Chael 0 : Checkig TX eady status... Ifo: tx_eady = 1 INFO: Chael 0: Release RX Reset Ifo: Check RX Ready Attempt: 1 INFO: Chael 0 : Checkig RX eady status... Ifo: x_eady = 1 INFO: Chael 0 : Checkig RX PCS eady status... Ifo: x_pcs_eady = 1 Ifo:Ifo: Chael: 0 Cofiguig DL .... Ifo Chael: 0 sedig packets i pogess, waitig fo checke pass *** Ifo Chael: 0 waitig fo measue_valid to asset... INFO: Chael 0 : Checkig hypefame syc status... INFO: hypefame syc asseted INFO: Chael 0 : Checkig RT cout doe status... INFO: RT cout doe asseted Chael 0 : Read Detemeistic latecy couts Chael 0 : Get checke_pass status: Checke value = 1 Checke status = Passed! ** ***************************************** INFO: Chael 0: Set TX Reset INFO: Chael 0 : Checkig tx eset ack status... INFO: TX fully i eset state INFO: Chael 0: Set RX Reset INFO: Chael 0 : Checkig x eset ack status... INFO: RX fully i eset state Ifo: Chael: 0 Cofiguig ED to CPRI 9P8G .... Ifo: Wait fo DR Ready.... Ifo: Tigge DR iteupt Ifo: Wait fo DR iteupt Ack.... Ifo: DR Request ackowledged Ifo: Wait fo DR Cofig to be doe.... Ifo: DONE Recofigue to 9P8G. INFO: Chael 0: Cofiguig cpi_speed Ifo: Chael: 0 Loop: 0 De-assetig eset to CPRI 9P8G .... INFO: Chael 0: Release TX Reset Ifo: Check TX Ready Attempt: 1 INFO: Chael 0 : Checkig TX eady status... Ifo: tx_eady = 1 INFO: Chael 0: Release RX Reset Ifo: Check RX Ready Attempt: 1 INFO: Chael 0 : Checkig RX eady status... Ifo: x_eady = 1 Ifo:Ifo: Chael: 0 Cofiguig DL .... Ifo Chael: 0 sedig packets i pogess, waitig fo checke pass *** Ifo Chael: 0 waitig fo measue_valid to asset... INFO: Chael 0 : Checkig hypefame syc status... INFO: hypefame syc asseted INFO: Chael 0 : Checkig RT cout doe status... INFO: RT cout doe asseted Chael 0 : Read Detemeistic latecy couts Chael 0 : Get checke_pass status: Checke value = 1 Checke status = Passed! ** ***************************************** INFO: Chael 0: Set TX Reset INFO: Chael 0 : Checkig tx eset ack status... INFO: TX fully i eset state INFO: Chael 0: Set RX Reset INFO: Chael 0 : Checkig x eset ack status... INFO: RX fully i eset state Ifo: Chael: 0 Cofiguig ED to CPRI 4P9G .... Ifo: Wait fo DR Ready.... Ifo: Tigge DR iteupt Ifo: Wait fo DR iteupt Ack.... Ifo: DR Request ackowledged Ifo: Wait fo DR Cofig to be doe.... Ifo: DONE Recofigue to 4P9G. INFO: Chael 0: Cofiguig cpi_speed Ifo: Chael: 0 Loop: 0 De-assetig eset to CPRI 4P9G .... INFO: Chael 0: Release TX Reset Ifo: Check TX Ready Attempt: 1 INFO: Chael 0 : Checkig TX eady status... Ifo: tx_eady = 1 INFO: Chael 0: Release RX Reset Ifo: Check RX Ready Attempt: 1 INFO: Chael 0 : Checkig RX eady status... Ifo: x_eady = 1 Ifo:Ifo: Chael: 0 Cofiguig DL .... Ifo Chael: 0 sedig packets i pogess, waitig fo checke pass *** Ifo Chael: 0 waitig fo measue_valid to asset... INFO: Chael 0 : Checkig hypefame syc status... INFO: hypefame syc asseted INFO: Chael 0 : Checkig RT cout doe status... INFO: RT cout doe asseted Chael 0 : Read Detemeistic latecy couts Chael 0 : Get checke_pass status: Checke value = 1 Checke status = Passed! ** ***************************************** INFO: Chael 0: Set TX Reset INFO: Chael 0 : Checkig tx eset ack status... INFO: TX fully i eset state INFO: Chael 0: Set RX Reset INFO: Chael 0 : Checkig x eset ack status... INFO: RX fully i eset state Ifo: Chael: 0 Cofiguig ED to CPRI 2P4G .... Ifo: Wait fo DR Ready.... Ifo: Tigge DR iteupt Ifo: Wait fo DR iteupt Ack.... Ifo: DR Request ackowledged Ifo: Wait fo DR Cofig to be doe.... Ifo: DONE Recofigue to 2P4G. INFO: Chael 0: Cofiguig cpi_speed Ifo: Chael: 0 Loop: 0 De-assetig eset to CPRI 2P4G .... INFO: Chael 0: Release TX Reset Ifo: Check TX Ready Attempt: 1 INFO: Chael 0 : Checkig TX eady status... Ifo: tx_eady = 1 INFO: Chael 0: Release RX Reset Ifo: Check RX Ready Attempt: 1 INFO: Chael 0 : Checkig RX eady status... Ifo: x_eady = 1 Ifo:Ifo: Chael: 0 Cofiguig DL .... Ifo Chael: 0 sedig packets i pogess, waitig fo checke pass *** Ifo Chael: 0 waitig fo measue_valid to asset... INFO: Chael 0 : Checkig hypefame syc status... INFO: hypefame syc asseted INFO: Chael 0 : Checkig RT cout doe status... INFO: RT cout doe asseted Chael 0 : Read Detemeistic latecy couts Chael 0 : Get checke_pass status: Checke value = 1 Checke status = Passed! ** ***************************************** INFO: Chael 0: Set TX Reset INFO: Chael 0 : Checkig tx eset ack status... INFO: TX fully i eset state INFO: Chael 0: Set RX Reset INFO: Chael 0 : Checkig x eset ack status... INFO: RX fully i eset state Ifo: Chael: 0 Cofiguig ED to CPRI 24G_RSFEC .... Ifo: Wait fo DR Ready.... Ifo: Tigge DR iteupt Ifo: Wait fo DR iteupt Ack.... Ifo: DR Request ackowledged Ifo: Wait fo DR Cofig to be doe.... Ifo: DONE Recofigue to 24G_RSFEC. INFO: Chael 0: Cofiguig cpi_speed Ifo: Chael: 0 Loop: 0 De-assetig eset to CPRI 24G_RSFEC .... INFO: Chael 0: Release TX Reset Ifo: Check TX Ready Attempt: 1 INFO: Chael 0 : Checkig TX eady status... Ifo: tx_eady = 1 INFO: Chael 0: Release RX Reset Ifo: Check RX Ready Attempt: 1 INFO: Chael 0 : Checkig RX eady status... Ifo: x_eady = 1 INFO: Chael 0 : Checkig RX PCS eady status... Ifo: x_pcs_eady = 1 Ifo:Ifo: Chael: 0 Cofiguig DL .... Ifo:Ifo: Chael: 0 Pogamig RSFEC WA ito DL coute .... Ifo:Ifo: Chael: 0 Statig DL .... Ifo Chael: 0 sedig packets i pogess, waitig fo checke pass *** Ifo Chael: 0 waitig fo measue_valid to asset... INFO: Chael 0 : Checkig hypefame syc status... INFO: hypefame syc asseted INFO: Chael 0 : Checkig RT cout doe status... INFO: RT cout doe asseted Chael 0 : Read Detemeistic latecy couts Chael 0 : Get checke_pass status: Checke value = 0 Checke status = Passed! ** ***************************************** Ifo: Ed of ftile_cpi_d_test Ifo: Test <ftile_cpi_d_test> Passed