F-Tile Dynamic Reconfiguration Design Example User Guide

Download PDF
ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.3

The F-Tile Dyamic Recofiguatio IP povides a simulatio testbech ad hadwae desig example that suppots compilatio ad simulatio. Whe you geeate the desig example, the paamete edito automatically ceates the files ecessay to simulate, compile, ad test the desig i hadwae.

Itel® also povides a compilatio-oly example poject that you ca use to quickly estimate IP coe aea ad timig.

Figue 1. Developmet Steps fo the Desig Example
The F-Tile Dyamic Recofiguatio desig example suppots the followig desig vaiats:
Table 1.  Suppoted Desig Example Vaiats
Potocol Base Vaiat Taget Vaiats
CPRI 24G CPRI with RS-FEC 1.2G CPRI
2.4G CPRI
3G CPRI
4.9G CPRI
6G CPRI
9.8G CPRI
10G CPRI
10G CPRI with RS-FEC
12G CPRI
12G CPRI with RS-FEC
24G CPRI
24G CPRI with RS-FEC
Etheet 100G-4 with RS-FEC 100G-4 with RS-FEC
100G-4
100G-2 with RS-FEC
2x50G-1 with RS-FEC
4x25G-1 with RS-FEC
4x25G-1
25G-1 with RS-FEC 25G-1 with RS-FEC
10G-1
400G-8 with RS-FEC 400G-8 with RS-FEC
2x200G-4 with RS-FEC
4x100G-2 with RS-FEC
100G-4 with RS-FEC ad PTP 1 100G-4 with RS-FEC ad PTP
100G-4 with PTP
100G-2 with RS-FEC ad PTP
2x50G-1 with RS-FEC ad PTP
4x25G-1 with RS-FEC ad PTP
4x25G-1 with PTP
25G-1 with RS-FEC ad PTP 2 25G-1 with RS-FEC ad PTP
10G-1 with PTP
400G-8 with RS-FEC ad PTP2 400G-8 with RS-FEC ad PTP
2x200G-4 with RS-FEC ad PTP
4x100G-2 with RS-FEC ad PTP
FHT 400G-4 with RS-FEC FHT 400G-4 with RS-FEC
FHT 1x200G-4 with RS-FEC
FHT 2x200G-2 with RS-FEC
FHT 2x100G-2 with RS-FEC
FHT 4x100G-1 with RS-FEC
PMA/FEC Diect PHY 53.125G 53.125G
53.125G with RS-FEC
25.7815G
24.33024G
10.3125G
10.1376G
9.8304G
4.9152G
2.4576G
400G-8 with RS-FEC 1x400G-8 with RS-FEC (PAM4) FEC Diect (544,514)
2x200G-4 with RS-FEC (PAM4) FEC Diect (544,514)
2x100G-4 with RS-FEC (NRZ) FEC Diect (528,514)
Etheet to CPRI 25G-1 with RS-FEC 25G-1 with RS-FEC
10G-1
24G CPRI with RS-FEC
10G CPRI
9.8G CPRI
4.9G CPRI
2.4G CPRI
25G-1 with RS-FEC (with 1GE) 25G-1 with RS-FEC
10G-1
1G-1
24G CPRI with RS-FEC
10G CPRI
9.8G CPRI
4.9G CPRI
2.4G CPRI

25G-1 PTP2 with RS-FEC (with 1GE PTP)

25G-1 with RS-FEC ad PTP
10G-1 with PTP
1G-1 with PTP
24G CPRI with RS-FEC
10G CPRI
9.8G CPRI
4.9G CPRI
2.4G CPRI
Note: Etheet vaiats suppot AN/LT as optioal.

Sectio Cotet
Hadwae ad Softwae Requiemets
Geeatig the Desig
Diectoy Stuctue
Compilig the Compilatio-Oly Poject
Simulatig the Desig Example Testbech
Compilig ad Cofiguig the Desig Example i Hadwae
Testig the Hadwae Desig Example

Related Ifomatio
1 Basic Accuacy Mode
2 Advaced Accuacy Mode
Level Two Title