ID
710582
Date
4/11/2024
Public
Visible to Intel only — GUID: lvz1634753429101
Ixiasoft
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Enabled Auto-Negotiation and Link Training
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
Visible to Intel only — GUID: lvz1634753429101
Ixiasoft
1. Quick Start Guide
Updated for: |
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Intel® Quartus® Prime Design Suite 24.1 |
The F-Tile Dynamic Reconfiguration IP provides a simulation testbench and hardware design example that supports compilation and simulation. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Intel® also provides a compilation-only example project that you can use to quickly estimate IP core area and timing.
Figure 1. Development Steps for the Design Example
The F-Tile Dynamic Reconfiguration design example supports the following design variants:
Protocol | Base Variant | Target Variants |
---|---|---|
CPRI | 24G CPRI with RS-FEC | 1.2G CPRI |
2.4G CPRI | ||
3G CPRI | ||
4.9G CPRI | ||
6G CPRI | ||
9.8G CPRI | ||
10G CPRI | ||
10G CPRI with RS-FEC | ||
12G CPRI | ||
12G CPRI with RS-FEC | ||
24G CPRI | ||
24G CPRI with RS-FEC | ||
Ethernet | 100G-4 with RS-FEC | 100G-4 with RS-FEC |
100G-4 | ||
100G-2 with RS-FEC | ||
2x50G-1 with RS-FEC | ||
4x25G-1 with RS-FEC | ||
4x25G-1 | ||
25G-1 with RS-FEC | 25G-1 with RS-FEC | |
10G-1 | ||
400G-8 with RS-FEC | 400G-8 with RS-FEC | |
2x200G-4 with RS-FEC | ||
4x100G-2 with RS-FEC | ||
100G-4 with RS-FEC and PTP 1 | 100G-4 with RS-FEC and PTP | |
100G-4 with PTP | ||
100G-2 with RS-FEC and PTP | ||
2x50G-1 with RS-FEC and PTP | ||
4x25G-1 with RS-FEC and PTP | ||
4x25G-1 with PTP | ||
25G-1 with RS-FEC and PTP 2 | 25G-1 with RS-FEC and PTP | |
10G-1 with PTP | ||
400G-8 with RS-FEC and PTP2 | 400G-8 with RS-FEC and PTP | |
2x200G-4 with RS-FEC and PTP | ||
4x100G-2 with RS-FEC and PTP | ||
FHT 400G-4 with RS-FEC | FHT 400G-4 with RS-FEC | |
FHT 1x200G-4 with RS-FEC | ||
FHT 2x200G-2 with RS-FEC | ||
FHT 2x100G-2 with RS-FEC | ||
FHT 4x100G-1 with RS-FEC | ||
PMA/FEC Direct PHY | 53.125G | 53.125G |
53.125G with RS-FEC | ||
25.7815G | ||
24.33024G | ||
10.3125G | ||
10.1376G | ||
9.8304G | ||
4.9152G | ||
2.4576G | ||
400G-8 with RS-FEC | 1x400G-8 with RS-FEC (PAM4) FEC Direct (544,514) | |
2x200G-4 with RS-FEC (PAM4) FEC Direct (544,514) | ||
2x100G-4 with RS-FEC (NRZ) FEC Direct (528,514) | ||
Ethernet to CPRI | 25G-1 with RS-FEC | 25G-1 with RS-FEC |
10G-1 | ||
24G CPRI with RS-FEC | ||
10G CPRI | ||
9.8G CPRI | ||
4.9G CPRI | ||
2.4G CPRI | ||
25G-1 with RS-FEC (with 1GE) | 25G-1 with RS-FEC | |
10G-1 | ||
1G-1 | ||
24G CPRI with RS-FEC | ||
10G CPRI | ||
9.8G CPRI | ||
4.9G CPRI | ||
2.4G CPRI | ||
25G-1 PTP2 with RS-FEC (with 1GE PTP) |
25G-1 with RS-FEC and PTP | |
10G-1 with PTP | ||
1G-1 with PTP | ||
24G CPRI with RS-FEC | ||
10G CPRI | ||
9.8G CPRI | ||
4.9G CPRI | ||
2.4G CPRI |
Note: Ethernet variants support AN/LT as optional.
Section Content
Hardware and Software Requirements
Generating the Design
Directory Structure
Compiling the Compilation-Only Project
Simulating the Design Example Testbench
Compiling and Configuring the Design Example in Hardware
Testing the Hardware Design Example
1 Basic Accuracy Mode
2 Advanced Accuracy Mode