RapidIO Intel FPGA IP User Guide

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ID 683884
Date 9/15/2021
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Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the RapidIO Intel FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Signals 6. Software Interface 7. Testbench 8. Platform Designer (Standard) Design Example 9. RapidIO Intel FPGA IP User Guide Archives 10. Document Revision History for the RapidIO Intel® FPGA IP User Guide A. Initialization Sequence B. Porting a RapidIO Design from the Previous Version of Software
1. About the RapidIO Intel FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grades 1.6. Release Information
1.1. Features x
1.1.1. Supported Transactions
1.3. IP Core Verification x
1.3.1. Simulation Testing 1.3.2. Hardware Testing 1.3.3. Interoperability Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generating IP Cores 2.3. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition) 2.4. RapidIO IP Core Testbench Files 2.5. Simulating IP Cores 2.6. Integrating Your IP Core in Your Design 2.7. Specifying Timing Constraints 2.8. Compiling the Full Design and Programming the FPGA 2.9. Instantiating Multiple RapidIO IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Generating IP Cores x
2.2.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.5. Simulating IP Cores x
2.5.1. Simulating the Testbench with the ModelSim Simulator 2.5.2. Simulating the Testbench with the VCS Simulator 2.5.3. Simulating the Testbench with the Xcelium Simulator
2.6. Integrating Your IP Core in Your Design x
2.6.1. Calibration Clock 2.6.2. Dynamic Transceiver Reconfiguration Controller 2.6.3. Transceiver Settings 2.6.4. Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations 2.6.5. External Transceiver PLL 2.6.6. Transceiver PHY Reset Controller for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations
2.9. Instantiating Multiple RapidIO IP Cores x
2.9.1. Clock and Signal Requirements for Arria® V, Cyclone® V, and Stratix® V Variations 2.9.2. Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations 2.9.3. Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances 2.9.4. Sourcing Multiple Tcl Scripts for Variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX
3. Parameter Settings x
3.1. Physical Layer Settings 3.2. Transport and Maintenance Settings 3.3. I/O and Doorbell Settings 3.4. Capability Registers Settings
3.1. Physical Layer Settings x
3.1.1. Device Options 3.1.2. Data Settings 3.1.3. Receive Priority Retry Thresholds 3.1.4. Transceiver Settings
3.2. Transport and Maintenance Settings x
3.2.1. Transport Layer 3.2.2. Input/Output Maintenance Logical Layer Module 3.2.3. Port Write
3.3. I/O and Doorbell Settings x
3.3.1. I/O Logical Layer Interfaces 3.3.2. I/O Slave Address Width 3.3.3. I/O Read and Write Order Preservation 3.3.4. Avalon® -MM Master 3.3.5. Avalon® -MM Slave 3.3.6. Doorbell Slave
3.4. Capability Registers Settings x
3.4.1. Device Registers 3.4.2. Assembly Registers 3.4.3. Processing Element Features 3.4.4. Switch Support 3.4.5. Data Messages
4. Functional Description x
4.1. Interfaces 4.2. Clocking and Reset Structure 4.3. Physical Layer 4.4. Transport Layer 4.5. Logical Layer Modules 4.6. Error Detection and Management
4.1. Interfaces x
4.1.1. RapidIO Interface 4.1.2. Avalon® Memory Mapped ( Avalon® -MM) Master and Slave Interfaces 4.1.3. Avalon® Streaming ( Avalon® -ST) Interface
4.1.2. Avalon® Memory Mapped ( Avalon® -MM) Master and Slave Interfaces x
4.1.2.1. Avalon® -MM Interface Widths in the RapidIO IP Core 4.1.2.2. Avalon® -MM Interface Byte Ordering
4.2. Clocking and Reset Structure x
4.2.1. RapidIO IP Core Clocking 4.2.2. Reset for RapidIO IP Cores
4.2.1. RapidIO IP Core Clocking x
4.2.1.1. Avalon® System Clock 4.2.1.2. Reference Clock 4.2.1.3. Other Input Clocks 4.2.1.4. Clock Domains 4.2.1.5. Baud Rates and Clock Frequencies
4.2.2. Reset for RapidIO IP Cores x
4.2.2.1. General RapidIO Reset Signal Requirements 4.2.2.2. Reset Controller 4.2.2.3. Reset Requirements for Arria® V, Cyclone® V, and Stratix® V Variations 4.2.2.4. Reset Requirements for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations 4.2.2.5. RapidIO IP Core Reset Behavior
4.3. Physical Layer x
4.3.1. Features 4.3.2. Physical Layer Architecture 4.3.3. Low-level Interface Receiver 4.3.4. Low-Level Interface Transmitter 4.3.5. Protocol and Flow Control Engine 4.3.6. Physical Layer Receive Buffer 4.3.7. Physical Layer Transmit Buffer
4.3.3. Low-level Interface Receiver x
4.3.3.1. Receiver Transceiver 4.3.3.2. CRC Checking and Removal
4.3.4. Low-Level Interface Transmitter x
4.3.4.1. Transmitter Transceiver
4.3.6. Physical Layer Receive Buffer x
4.3.6.1. Error Conditions that Flush the Receive Buffer 4.3.6.2. Error Conditions Flagged for the Transport Layer 4.3.6.3. Receive Priority Threshold Values
4.3.7. Physical Layer Transmit Buffer x
4.3.7.1. Transmit and Retransmit Queues 4.3.7.2. Error Conditions that Flush the Transmit Buffer 4.3.7.3. Forced Compensation Sequence Insertion
4.4. Transport Layer x
4.4.1. Receiver 4.4.2. Transaction ID Ranges 4.4.3. Transmitter
4.5. Logical Layer Modules x
4.5.1. Concentrator Register Module 4.5.2. Maintenance Module 4.5.3. Input/Output Logical Layer Modules 4.5.4. Doorbell Module 4.5.5. Avalon® -ST Pass-Through Interface
4.5.2. Maintenance Module x
4.5.2.1. Maintenance Register 4.5.2.2. Maintenance Slave Processor 4.5.2.3. Maintenance Master Processor 4.5.2.4. Port-Write Processor 4.5.2.5. Maintenance Module Error Handling
4.5.2.4. Port-Write Processor x
4.5.2.4.1. Port-Write Transmission 4.5.2.4.2. Port-Write Reception
4.5.3. Input/Output Logical Layer Modules x
4.5.3.1. Input/Output Avalon® -MM Master Module 4.5.3.2. Input/Output Avalon® -MM Master Module Timing Diagrams 4.5.3.3. Input/Output Avalon® -MM Slave Module 4.5.3.4. Avalon® -MM Burstcount and Byteenable Encoding in RapidIO Packets 4.5.3.5. Input/Output Avalon® -MM Slave Module Timing Diagrams
4.5.3.1. Input/Output Avalon® -MM Master Module x
4.5.3.1.1. Input/Output Avalon® -MM Master Address Mapping Windows
4.5.3.3. Input/Output Avalon® -MM Slave Module x
4.5.3.3.1. Keeping Track of I/O Write Transactions 4.5.3.3.2. Input/Output Avalon® -MM Slave Address Mapping Windows 4.5.3.3.3. Input/Output Slave Translation Window Example 4.5.3.3.4. Translation Window 0 4.5.3.3.5. Translation Window 1 4.5.3.3.6. Translation Window 2
4.5.4. Doorbell Module x
4.5.4.1. Doorbell Module Block Diagram 4.5.4.2. Preserving Transaction Order 4.5.4.3. Doorbell Message Generation 4.5.4.4. Doorbell Message Reception
4.5.5. Avalon® -ST Pass-Through Interface x
4.5.5.1. Pass-Through Interface Examples
4.6. Error Detection and Management x
4.6.1. Physical Layer Error Management 4.6.2. Logical Layer Error Management 4.6.3. Avalon® -ST Pass-Through Interface
4.6.1. Physical Layer Error Management x
4.6.1.1. Protocol Violations 4.6.1.2. Fatal Errors
4.6.2. Logical Layer Error Management x
4.6.2.1. Maintenance Avalon® -MM Slave 4.6.2.2. Maintenance Avalon® -MM Master 4.6.2.3. Port-Write Reception Module 4.6.2.4. Port-Write Transmission Module 4.6.2.5. Input/Output Avalon® -MM Slave 4.6.2.6. Input/Output Avalon® -MM Master
4.6.2.1. Maintenance Avalon® -MM Slave x
4.6.2.1.1. Standard Error Management Registers 4.6.2.1.2. Registers in the Implementation Defined Space 4.6.2.1.3. Maintenance Avalon® -MM Slave Interface's Error Indication Signal
4.6.2.5. Input/Output Avalon® -MM Slave x
4.6.2.5.1. Standard Error Management Registers 4.6.2.5.2. Registers in the Implementation Defined Space 4.6.2.5.3. The Avalon® -MM Slave Interface's Error Indication Signal
4.6.2.6. Input/Output Avalon® -MM Master x
4.6.2.6.1. Standard Error Management Registers 4.6.2.6.2. Response Packets with ERROR Status
5. Signals x
5.1. Physical Layer Signals 5.2. Transport and Logical Layer Signals
5.1. Physical Layer Signals x
5.1.1. Status Packet and Error Monitoring Signals 5.1.2. Multicast Event Signals 5.1.3. Receive Priority Retry Threshold-Related Signals 5.1.4. Physical Layer Buffer Status Signals 5.1.5. Transceiver Signals 5.1.6. Register-Related Signals
5.2. Transport and Logical Layer Signals x
5.2.1. Avalon® -MM Interface Signals 5.2.2. Avalon® -ST Pass-Through Interface Signals 5.2.3. Error Management Extension Signals 5.2.4. Packet and Error Monitoring Signal for the Transport Layer
6. Software Interface x
6.1. Physical Layer Registers 6.2. Transport and Logical Layer Registers
6.2. Transport and Logical Layer Registers x
6.2.1. Capability Registers (CARs) 6.2.2. Command and Status Registers (CSRs) 6.2.3. Maintenance Interrupt Control Registers 6.2.4. Receive Maintenance Registers 6.2.5. Transmit Maintenance Registers 6.2.6. Transmit Port-Write Registers 6.2.7. Receive Port-Write Registers 6.2.8. Input/Output Master Address Mapping Registers 6.2.9. Input/Output Slave Mapping Registers 6.2.10. Input/Output Slave Interrupts 6.2.11. Transport Layer Feature Register 6.2.12. Error Management Registers 6.2.13. Doorbell Message Registers
7. Testbench x
7.1. Reset, Initialization, and Configuration 7.2. Maintenance Write and Read Transactions 7.3. SWRITE Transactions 7.4. NWRITE_R Transactions 7.5. NWRITE Transactions 7.6. NREAD Transactions 7.7. Doorbell Transactions 7.8. Doorbell and Write Transactions With Transaction Order Preservation 7.9. Port-Write Transactions 7.10. Transactions Across the Avalon® -ST Pass-Through Interface
8. Platform Designer (Standard) Design Example x
8.1. Creating a New Intel® Quartus® Prime Project 8.2. Running Platform Designer (Standard) 8.3. Simulating the System
8.2. Running Platform Designer (Standard) x
8.2.1. Adding and Parameterizing the RapidIO Component 8.2.2. Adding and Connecting Other System Components 8.2.3. Connecting Clocks and the System Components 8.2.4. Generating the System
8.2.2. Adding and Connecting Other System Components x
8.2.2.1. Adding the Master Maintenance BFM 8.2.2.2. Adding the Master I/O BFM 8.2.2.3. Adding the On-Chip Memory
8.2.3. Connecting Clocks and the System Components x
8.2.3.1. Connecting Unconnected Clocks 8.2.3.2. Connecting System Components 8.2.3.3. Assigning Addresses and Setting the Clock Frequency
B. Porting a RapidIO Design from the Previous Version of Software x
B.1. Upgrading a RapidIO Design Without Changing Device Family B.2. Upgrading a RapidIO Design to the Intel® Arria® 10 and Intel® Cyclone® 10 GX Device Families
Product Discontinuance Notification
1. About the RapidIO Intel FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. Platform Designer (Standard) Design Example
9. RapidIO Intel FPGA IP User Guide Archives
10. Document Revision History for the RapidIO Intel® FPGA IP User Guide
A. Initialization Sequence
B. Porting a RapidIO Design from the Previous Version of Software

5.1.5. Transceiver Signals

Transceiver signals are connected directly to the transceiver block. In some cases these signals must be shared by multiple transceiver blocks that are implemented in the same device.

Table 39.  Transceiver Signals
Signal Direction Description
cal_blk_clk 36 Input The Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX transceiver’s on-chip termination resistors are calibrated by a single calibration block. This circuitry requires a calibration clock. The frequency range of the cal_blk_clk is 10–125 MHz.

This signal is not present in Arria® V, Intel® Arria® 10, Cyclone® V, Intel® Cyclone® 10 GX, or Stratix® V variations.

phy_mgmt_clk36 Input Clocks the Custom PHY IP core software interface. The expected maximum frequency of this clock is 250 MHz.

This signal is present only in Arria® V, Cyclone® V, and Stratix® V variations.

phy_mgmt_clk_reset Input Resets the Custom PHY IP core. This signal is present only in Arria® V, Cyclone® V, and Stratix V variations.

phy_mgmt_clk_reset can be asserted asynchronously, but must stay asserted at least one clock cycle and must be de-asserted synchronously with phy_mgmt_clk. In addition, this signal must be driven by the same source as reset_n, to ensure that the two signals are asserted—but not deasserted—together. Fig: Circuit to Also Ensure Synchronous Assertion of phy_mgmt_clk_reset with reset_n shows how to enforce the synchronous assertion with reset_n and the minimal removal time and synchronous deassertion with phy_mgmt_clk. In addition, phy_mgmt_clk_reset should not be deasserted when the Transceiver Reconfiguration Controller reconfig_busy signal is high.

rxgxbclk Output Transceiver receiver clock (recovered clock).
reconfig_clk Input Reference clock for the dynamic reconfiguration controller. The frequency range for this clock is 2.5–50 MHz. If you use a dynamic reconfiguration block in your design to dynamically control the transceiver, then this clock is required by the dynamic reconfiguration block and the RapidIO IP core.

If no external dynamic reconfiguration block is used, this input should be tied low.

This signal is not present in Arria® V, Intel® Arria® 10, Cyclone® V, Intel® Cyclone® 10 GX, or Stratix® V variations.

reconfig_togxb Input Driven from an external dynamic reconfiguration block. Supports the selection of multiple transceiver channels for dynamic reconfiguration. Note that not using a dynamic reconfiguration block that enables offset cancellation results in a non-functional hardware design.

In Arria® V, Cyclone® V, and Stratix® V devices, the width of this bus is (C + 1) × 70, where C is the number of channels, 1, 2, or 4. This width supports communication from Reconfiguration Controller with C + 1 reconfiguration interfaces—one dedicated to each channel and another for the transceiver PLL—to the transceiver.

If you omit the Reconfiguration Controller from your simulation model, you must ensure all bits of this bus are tied to 0.

This signal is not present in Intel® Arria® 10 and Intel® Cyclone® 10 GX variations.

reconfig_fromgxb Output Driven to an external dynamic reconfiguration block. The bus identifies the transceiver channel whose settings are being transmitted to the dynamic reconfiguration block. If no external dynamic reconfiguration block is used, then this output bus can be left unconnected. However, not using a dynamic reconfiguration block that enables offset cancellation results in a non-functional hardware design.

In Arria® V, Cyclone® V, and Stratix® V devices, the width of this bus is (C + 1) × 46, where C is the number of channels, 1, 2, or 4. This width supports communication from the transceiver to C + 1 reconfiguration interfaces in Reconfiguration Controller, one interface dedicated to each channel and an additional interface for the transceiver PLL.

This signal is not present in Intel® Arria® 10 and Intel® Cyclone® 10 GX variations.

gxbpll_locked Output / Input Indicates the transceiver transmitter PLL is locked to the reference clock. In Intel® Arria® 10 and Intel® Cyclone® 10 GX variations, this is an input signal to the RapidIO IP core that is intended to be connected to the external PLL; in all other variations, this is an output signal from the transceiver PLL in the RapidIO IP core.
gxb_powerdown Input Transceiver block reset and power down. This resets and powers down all circuits in the transceiver block. This signal does not affect the refclk buffers and reference clock lines.

All the gxb_powerdown input signals of IP cores intended to be placed in the same quad should be tied together. The gxb_powerdown should be tied low or should remain asserted for at least 2 ms whenever it is asserted.

This signal is not present in Arria® V, Intel® Arria® 10, Cyclone® V, Intel® Cyclone® 10 GX, or Stratix® V variations.

rx_errdetect Output Transceiver 8B10B code group violation signal bus. The signal width depends on the IP core mode.
tx_bonding_clocks_ch0[5:0] Input Transceiver channel TX input clocks for RapidIO lane 0. This signal is available only in Intel® Arria® 10 and Intel® Cyclone® 10 GX variations. Each transceiver channel that corresponds to a RapidIO lane has six input clock bits. The bits are expected to be driven from a TX PLL.
tx_bonding_clocks_ch1[5:0] Input Transceiver channel TX input clocks for RapidIO lane 1. This signal is available only in Intel® Arria® 10 and Intel® Cyclone® 10 GX 2x and 4x variations. Each transceiver channel that corresponds to a RapidIO lane has six input clock bits. The bits are expected to be driven from a TX PLL.
tx_bonding_clocks_ch2[5:0] Input Transceiver channel TX input clocks for RapidIO lane 2. This signal is available only in Intel® Arria® 10 and Intel® Cyclone® 10 GX 4x variations. Each transceiver channel that corresponds to a RapidIO lane has six input clock bits. The bits are expected to be driven from a TX PLL.
tx_bonding_clocks_ch3[5:0] Input Transceiver channel TX input clocks for RapidIO lane 3. This signal is available only in Intel® Arria® 10 and Intel® Cyclone® 10 GX 4x variations. Each transceiver channel that corresponds to a RapidIO lane has six input clock bits. The bits are expected to be driven from a TX PLL.
tx_analogreset
[<number of lanes>-1:0] Input

You must connect these signals to Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device. Connect each signal to the corresponding signal in the Transceiver PHY Reset Controller IP core.

These signals are available only in Intel® Arria® 10 and Intel® Cyclone® 10 GX IP core variations.

rx_analogreset
[<number of lanes>-1:0] Input
tx_digitalreset
[<number of lanes>-1:0] Input
rx_digitalreset
[<number of lanes>-1:0] Input
rx_is_lockedtodata
[<number of lanes>-1:0] Output
tx_cal_busy
[<number of lanes>-1:0] Output
rx_cal_busy
[<number of lanes>-1:0] Output

Each of these individual interfaces is an Avalon® -MM interface you use to access the hard registers for the corresponding transceiver channel on the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. These signals are available if you turn on Enable transceiver dynamic reconfiguration in the RapidIO parameter editor.

Table 40.   Intel® Arria® 10 and Intel® Cyclone® 10 GX Transceiver Dynamic Reconfiguration Avalon® -MM Interface Signals
Signal Direction Description
reconfig_clk_ch0 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration interface clock for the transceiver channel configured for RapidIO lane 0.
reconfig_reset_ch0 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration interface reset for the transceiver channel configured for RapidIO lane 0.
reconfig_waitrequest_ch0 Output Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave wait request for the transceiver channel configured for RapidIO lane 0. The RapidIO IP core uses this signal to stall the requestor on the interconnect.
reconfig_read_ch0 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave read request for the transceiver channel configured for RapidIO lane 0.
reconfig_write_ch0 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave write request for the transceiver channel configured for RapidIO lane 0.
reconfig_address_ch0[9:0] Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave address bus for the transceiver channel configured for RapidIO lane 0. The address is a word address, not a byte address.
reconfig_writedata_ch0[31:0] Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave write data bus for the transceiver channel configured for RapidIO lane 0.
reconfig_readdata_ch0[31:0] Output Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave read data bus for the transceiver channel configured for RapidIO lane 0.
reconfig_clk_ch1 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration interface clock for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_reset_ch1 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration interface reset for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_waitrequest_ch1 Output Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave wait request for the transceiver channel configured for RapidIO lane 1. The RapidIO IP core uses this signal to stall the requestor on the interconnect.

This signal is available only in 2x and 4x variations.

reconfig_read_ch1 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave read request for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_write_ch1 Input Intel® Arria® 10 dynamic reconfiguration slave write request for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_address_ch1[9:0] Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave address bus for the transceiver channel configured for RapidIO lane 1. The address is a word address, not a byte address.

This signal is available only in 2x and 4x variations.

reconfig_writedata_ch1[31:0] Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave write data bus for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_readdata_ch1[31:0] Output Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave read data bus for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_clk_ch2 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration interface clock for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_reset_ch2 Input Intel® Arria® 10 dynamic reconfiguration interface reset for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_waitrequest_ch2 Output Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave wait request for the transceiver channel configured for RapidIO lane 2. The RapidIO IP core uses this signal to stall the requestor on the interconnect.

This signal is available only in 4x variations.

reconfig_read_ch2 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave read request for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_write_ch2 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave write request for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_address_ch2[9:0] Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave address bus for the transceiver channel configured for RapidIO lane 2. The address is a word address, not a byte address.

This signal is available only in 4x variations.

reconfig_writedata_ch2[31:0] Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave write data bus for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_readdata_ch2[31:0] Output Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave read data bus for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_clk_ch3 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration interface clock for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_reset_ch3 Input Intel® Arria® 10 dynamic reconfiguration interface reset for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_waitrequest_ch3 Output Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave wait request for the transceiver channel configured for RapidIO lane 3. The RapidIO IP core uses this signal to stall the requestor on the interconnect.

This signal is available only in 4x variations.

reconfig_read_ch3 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave read request for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_write_ch3 Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave write request for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_address_ch3[9:0] Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave address bus for the transceiver channel configured for RapidIO lane 3. The address is a word address, not a byte address.

This signal is available only in 4x variations.

reconfig_writedata_ch3[31:0] Input Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave write data bus for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_readdata_ch3[31:0] Output Intel® Arria® 10/ Intel® Cyclone® 10 GX dynamic reconfiguration slave read data bus for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.

In addition to customization of the transceiver through the parameter editor (in variations that target a device for which the transceivers are configured with the ALTGX megafunction, and not with the Transceiver PHY IP core), you can use the transceiver reconfiguration block to dynamically modify the parameter interface. The dynamic reconfiguration block lets you reconfigure the following PMA settings:

  • Pre-emphasis
  • Equalization
  • Offset cancellation
  • VOD on a per channel basis

The dynamic reconfiguration block is required for many device families, including Arria® V, Cyclone® V, and Stratix® V devices. For details, go to the appropriate device handbook. For more information about offset cancellation, refer to the relevant device handbook.

Related Information
36 You connect this clock inside the Platform Designer (Standard) tool. If you connect it to an external clock, a port with the name of that external clock is added to your Platform Designer (Standard) system and this clock is connected to it.
Level Two Title