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1. About the RapidIO Intel FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. Platform Designer (Standard) Design Example
9. RapidIO Intel FPGA IP User Guide Archives
10. Document Revision History for the RapidIO Intel® FPGA IP User Guide
A. Initialization Sequence
B. Porting a RapidIO Design from the Previous Version of Software
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Generating IP Cores
2.3. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.4. RapidIO IP Core Testbench Files
2.5. Simulating IP Cores
2.6. Integrating Your IP Core in Your Design
2.7. Specifying Timing Constraints
2.8. Compiling the Full Design and Programming the FPGA
2.9. Instantiating Multiple RapidIO IP Cores
2.6.1. Calibration Clock
2.6.2. Dynamic Transceiver Reconfiguration Controller
2.6.3. Transceiver Settings
2.6.4. Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations
2.6.5. External Transceiver PLL
2.6.6. Transceiver PHY Reset Controller for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations
2.9.1. Clock and Signal Requirements for Arria® V, Cyclone® V, and Stratix® V Variations
2.9.2. Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations
2.9.3. Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances
2.9.4. Sourcing Multiple Tcl Scripts for Variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX
6.2.1. Capability Registers (CARs)
6.2.2. Command and Status Registers (CSRs)
6.2.3. Maintenance Interrupt Control Registers
6.2.4. Receive Maintenance Registers
6.2.5. Transmit Maintenance Registers
6.2.6. Transmit Port-Write Registers
6.2.7. Receive Port-Write Registers
6.2.8. Input/Output Master Address Mapping Registers
6.2.9. Input/Output Slave Mapping Registers
6.2.10. Input/Output Slave Interrupts
6.2.11. Transport Layer Feature Register
6.2.12. Error Management Registers
6.2.13. Doorbell Message Registers
7.1. Reset, Initialization, and Configuration
7.2. Maintenance Write and Read Transactions
7.3. SWRITE Transactions
7.4. NWRITE_R Transactions
7.5. NWRITE Transactions
7.6. NREAD Transactions
7.7. Doorbell Transactions
7.8. Doorbell and Write Transactions With Transaction Order Preservation
7.9. Port-Write Transactions
7.10. Transactions Across the Avalon® -ST Pass-Through Interface
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6.2.12. Error Management Registers
These registers can be used by software to diagnose problems with packets that are received by the local endpoint. If enabled, the detected error triggers the assertion of sys_mnt_s_irq. Information about the packet that caused the error is captured in the capture registers. After an error condition is detected, the information is captured and the capture registers are locked until the Error Detect CSR is cleared. Upon being cleared, the capture registers are ready to capture a new packet that exhibits an error condition.
Field | Bits | Access | Function | Default |
---|---|---|---|---|
IO_ERROR_RSP | [31] | RW | Received a response of ERROR for an I/O Logical Layer Request. | 1'b0 |
MSG_ERROR_RESPONSE | [30] | RW | Received a response of ERROR for a MSG Logical Layer Request. | 1'b0 |
GSM error response | [29] | RO | This feature is not supported. | 1'b0 |
MSG_FORMAT_ERROR | [28] | RW | Received MESSAGE packet data payload with an invalid size or segment. | 1'b0 |
ILL_TRAN_DECODE | [27] | RW | Received illegal fields in the request/response packet for a supported transaction. | 1'b0 |
ILL_TRAN_TARGET | [26] | RW | Received a packet that contained a destination ID that is not defined for this end point. | 1'b0 |
MSG_REQ_TIMEOUT | [25] | RW | A required message request has not been received within the specified time-out interval. | 1'b0 |
PKT_RSP_TIMEOUT | [24] | RW | A required response has not been received within the specified time-out interval. | 1'b0 |
UNSOLICIT_RSP | [23] | RW | An unsolicited/unexpected response packet was received. | 1'b0 |
UNSUPPORT_TRAN | [22] | RW | A transaction is received that is not supported in the Destination Operations CAR. | 1'b0 |
RSRV | [21:8] | RO | Reserved | 22'h0 |
Implementation Specific error | [7:0] | RO | This feature is not supported. | 8’b0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
IO_ERROR_RSP_EN | [31] | RW | Enable reporting of an I/O error response. Save and lock original request transaction information in all Logical/Transport Layer Capture CSRs. | 1'b0 |
MSG_ERROR_RESPONSE_EN | [30] | RW | Enable reporting of a Message error response. Save and lock original request transaction information in all Logical/Transport Layer Capture CSRs. | 1'b0 |
GSM error response enable | [29] | RO | This feature is not supported. | 1’b0 |
MSG_FORMAT_ERROR_EN | [28] | RW | Enable reporting of a message format error. Save and lock original request transaction information in all Logical/Transport Layer Capture CSRs. | 1’b0 |
ILL_TRAN_DECODE_EN | [27] | RW | Enable reporting of an illegal transaction decode error. Save and lock transaction capture information in Logical/Transport Layer Device ID and Control Capture CSRs. | 1'b0 |
ILL_TRAN_TARGET_EN | [26] | RW | Enable reporting of an illegal transaction target error. Save and lock transaction capture information in Logical/Transport Layer Device ID and Control Capture CSRs. | 1'b0 |
MSG_REQ_TIMEOUT_EN | [25] | RW | Enable reporting of a Message Request time-out error. Save and lock original request transaction information in Logical/Transport Layer Device ID and Control Capture CSRs for the last Message request segment packet received. | 1'b0 |
PKT_RSP_TIMEOUT_EN | [24] | RW | Enable reporting of a packet response time-out error. Save and lock original request address in Logical/Transport Layer Address Capture CSRs. Save and lock original request destination ID in Logical/Transport Layer Device ID Capture CSR. | 1'b0 |
UNSOLICIT_RSP_EN | [23] | RW | Enable reporting of an unsolicited response error. Save and lock transaction capture information in Logical/Transport Layer Device ID and Control Capture CSRs. | 1'b0 |
UNSUPPORT_TRAN_EN | [22] | RW | Enable report of an unsupported transaction error. Save and lock transaction capture information in Logical/Transport Layer Device ID and Control Capture CSRs. | 1'b0 |
RSRV | [21-8] | RO | Reserved | 14'h0 |
Implementation Specific error enable | [7-0] | RO | This feature is not supported. | 8’b0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
ADDRESS | [31:3] | RO | Bits 31 to 3 of the RapidIO address associated with the error. | 29'h0 |
RSRV | [2] | RO | Reserved | 1'b0 |
XAMSBS | [1:0] | RO | Extended address bits of the address associated with the error. | 2'h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
LARGE_DESTINATION_ID (MSB) | [31:24] | RO | Reserved if the system does not support 16-bit device ID. | 8'h0 |
RW | MSB of the Destination ID if the system supports 16-bit device ID. | |||
DESTINATION_ID | [23:16] | RO | The destination ID associated with the error. | 8'h0 |
LARGE_SOURCE_ID (MSB) | [15:8] | RO | Reserved if the system does not support 16-bit device ID. | 8'h0 |
RW | MSB of the Source ID if the system supports 16-bit device ID. | |||
SOURCE_ID | [7:0] | RO | The source ID associated with the error. | 8'h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
FTYPE | [31:28] | RO | Format type associated with the error. | 4'h0 |
TTYPE | [27:24] | RO | Transaction type associated with the error. | 4'h0 |
MSG_INFO | [23:16] | RO | Letter, mbox, and msgseg for the last message request received for the mailbox that had and error. | 8'h0 |
Implementation Specific | [15:0] | RO | Reserved for this implementation. | 16'h0 |