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1. About the RapidIO Intel FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. Platform Designer (Standard) Design Example
9. RapidIO Intel FPGA IP User Guide Archives
10. Document Revision History for the RapidIO Intel® FPGA IP User Guide
A. Initialization Sequence
B. Porting a RapidIO Design from the Previous Version of Software
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Generating IP Cores
2.3. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.4. RapidIO IP Core Testbench Files
2.5. Simulating IP Cores
2.6. Integrating Your IP Core in Your Design
2.7. Specifying Timing Constraints
2.8. Compiling the Full Design and Programming the FPGA
2.9. Instantiating Multiple RapidIO IP Cores
2.6.1. Calibration Clock
2.6.2. Dynamic Transceiver Reconfiguration Controller
2.6.3. Transceiver Settings
2.6.4. Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations
2.6.5. External Transceiver PLL
2.6.6. Transceiver PHY Reset Controller for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations
2.9.1. Clock and Signal Requirements for Arria® V, Cyclone® V, and Stratix® V Variations
2.9.2. Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations
2.9.3. Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances
2.9.4. Sourcing Multiple Tcl Scripts for Variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX
6.2.1. Capability Registers (CARs)
6.2.2. Command and Status Registers (CSRs)
6.2.3. Maintenance Interrupt Control Registers
6.2.4. Receive Maintenance Registers
6.2.5. Transmit Maintenance Registers
6.2.6. Transmit Port-Write Registers
6.2.7. Receive Port-Write Registers
6.2.8. Input/Output Master Address Mapping Registers
6.2.9. Input/Output Slave Mapping Registers
6.2.10. Input/Output Slave Interrupts
6.2.11. Transport Layer Feature Register
6.2.12. Error Management Registers
6.2.13. Doorbell Message Registers
7.1. Reset, Initialization, and Configuration
7.2. Maintenance Write and Read Transactions
7.3. SWRITE Transactions
7.4. NWRITE_R Transactions
7.5. NWRITE Transactions
7.6. NREAD Transactions
7.7. Doorbell Transactions
7.8. Doorbell and Write Transactions With Transaction Order Preservation
7.9. Port-Write Transactions
7.10. Transactions Across the Avalon® -ST Pass-Through Interface
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6.2.2. Command and Status Registers (CSRs)
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:3] | RO | Reserved | 29'h0 |
EXT_ADDR_CTRL | [2:0] | RO | Controls the number of address bits generated by the Processing element as a source and processed by the Processing element as the target of an operation. 'b100 – Processing element supports 66 bit addresses 'b010 – Processing element supports 50 bit addresses 'b001 – Processing element supports 34 bit addresses All other encodings reserved |
3'b001 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31] | RO | Reserved | 1'b0 |
LCSBA | [30:15] | RO | Reserved for a 34-bit local physical address | 16'h0 |
LCSBA | [14:0] | RO | Reserved for a 34-bit local physical address | 15'h0 |
Field56 | Bits | Access | Function | Default |
---|---|---|---|---|
LCSBA | [31] | RO | Reserved for a 34-bit local physical address | 1'b0 |
LCSBA | [30:0] | RW | Bits 33:4 of a 34-bit physical address | 31'h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:24] | RO | Reserved | 8'h0 |
DEVICE_ID 57 | [23:16] | RW | This is the base ID of the device in a small common transport system. | 8'hFF |
RO | Reserved if the system does not support 8-bit device ID. | |||
LARGE_DEVICE_ID 57 | [15:0] | RW | This is the base ID of the device in a large common transport system. | 16'hFFFF |
RO | Reserved if the system does not support 16-bit device ID. |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:16] | RO | Reserved | 16'h0 |
HOST_BASE_DEVICE_ID | [15:0] | RW58 | This is the base device ID for the processing element that is initializing this processing element. | 16'hFFFF |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
COMPONENT_TAG | [31:0] | RW | This is a component tag for the processing element. | 32'h0 |
56 The Local Configuration Space Base Address registers are hard coded to zero. If the Input/Output Avalon® -MM master interface is connected to the System Maintenance Avalon® -MM slave interface, regular read and write operations rather than MAINTENANCE operations, can be used to access the processing element's registers for configuration and maintenance.
57 In a small common transport system, the DEVICE_ID field is Read-Write and the LARGE_DEVICE_ID field is Read-only. In a large common transport system, the DEVICE_ID field is Read-only and the LARGE_DEVICE_ID field is Read-Write.
58 Write once; can be reset. See Part 3 of the RapidIO Specification Rev 2.1 for more information.