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1. About the RapidIO Intel FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. Platform Designer (Standard) Design Example
9. RapidIO Intel FPGA IP User Guide Archives
10. Document Revision History for the RapidIO Intel® FPGA IP User Guide
A. Initialization Sequence
B. Porting a RapidIO Design from the Previous Version of Software
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Generating IP Cores
2.3. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.4. RapidIO IP Core Testbench Files
2.5. Simulating IP Cores
2.6. Integrating Your IP Core in Your Design
2.7. Specifying Timing Constraints
2.8. Compiling the Full Design and Programming the FPGA
2.9. Instantiating Multiple RapidIO IP Cores
2.6.1. Calibration Clock
2.6.2. Dynamic Transceiver Reconfiguration Controller
2.6.3. Transceiver Settings
2.6.4. Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations
2.6.5. External Transceiver PLL
2.6.6. Transceiver PHY Reset Controller for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations
2.9.1. Clock and Signal Requirements for Arria® V, Cyclone® V, and Stratix® V Variations
2.9.2. Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations
2.9.3. Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances
2.9.4. Sourcing Multiple Tcl Scripts for Variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX
6.2.1. Capability Registers (CARs)
6.2.2. Command and Status Registers (CSRs)
6.2.3. Maintenance Interrupt Control Registers
6.2.4. Receive Maintenance Registers
6.2.5. Transmit Maintenance Registers
6.2.6. Transmit Port-Write Registers
6.2.7. Receive Port-Write Registers
6.2.8. Input/Output Master Address Mapping Registers
6.2.9. Input/Output Slave Mapping Registers
6.2.10. Input/Output Slave Interrupts
6.2.11. Transport Layer Feature Register
6.2.12. Error Management Registers
6.2.13. Doorbell Message Registers
7.1. Reset, Initialization, and Configuration
7.2. Maintenance Write and Read Transactions
7.3. SWRITE Transactions
7.4. NWRITE_R Transactions
7.5. NWRITE Transactions
7.6. NREAD Transactions
7.7. Doorbell Transactions
7.8. Doorbell and Write Transactions With Transaction Order Preservation
7.9. Port-Write Transactions
7.10. Transactions Across the Avalon® -ST Pass-Through Interface
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6.2.3. Maintenance Interrupt Control Registers
If any of these error conditions are detected and if the corresponding Interrupt Enable bit is set, the sys_mnt_s_irq signal is asserted.
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:7] | RO | Reserved | 25'h0 |
PORT_WRITE_ERROR | [6] | RW1C | Port-write error | 1'b0 |
PACKET_DROPPED | [5] | RW1C | A received port-write packet was dropped. A port-write packet is dropped under the following conditions:
|
1'b0 |
PACKET_STORED | [4] | RW1C | Indicates that the IP core has received a port-write packet and that the payload can be retrieved using the System Maintenance Avalon® -MM slave interface. | 1'b0 |
RSRV | [3] | RO | Reserved | 1'b0 |
RSRV | [2] | RO | Reserved | 1'b0 |
WRITE_OUT_OF_BOUNDS | [1] | RW1C | If the address of an Avalon® -MM write transfer presented at the Maintenance Avalon® -MM slave interface does not fall within any of the enabled Tx Maintenance Address translation windows, then it is considered out of bounds and this bit is set. | 1'b0 |
READ_OUT_OF_BOUNDS | [0] | RW1C | If the address of an Avalon® -MM read transfer presented at the Maintenance Avalon® -MM slave interface does not fall within any of the enabled Tx Maintenance Address translation windows, then it is considered out of bounds and this bit is set. | 1'b0 |
Field | Bit | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:7] | RO | Reserved | 25'h0 |
PORT_WRITE_ERROR | [6] | RW | Port-write error interrupt enable | 1'b0 |
RX_PACKET_DROPPED | [5] | RW | Rx port-write packet dropped interrupt enable | 1'b0 |
RX_PACKET_STORED | [4] | RW | Rx port-write packet stored in buffer interrupt enable | 1'b0 |
RSRV | [3:2] | RO | Reserved | 2'b00 |
WRITE_OUT_OF_BOUNDS | [1] | RW | Tx write request address out of bounds interrupt enable | 1'b0 |
READ_OUT_OF_BOUNDS | [0] | RW | Tx read request address out of bounds interrupt enable | 1'b0 |