Visible to Intel only — GUID: sai1490746648118
Ixiasoft
Visible to Intel only — GUID: sai1490746648118
Ixiasoft
4.5.1. Concentrator Register Module
The Concentrator module provides access to the Avalon® -MM slave interface and the RapidIO IP core register set. The interface supports simple reads and writes with variable latency. Accesses are to 32-bit words addressed by a 17-bit wide byte address. When accessed, the lower 2 bits of the address are ignored and assumed to be 0, which aligns the transactions to 4-byte words. The interface supports an interrupt line, sys_mnt_s_irq. When enabled, the following interrupts assert the sys_mnt_s_irq signal:
- Received port-write
- I/O read out of bounds
- I/O write out of bounds
- Invalid write
- Invalid write burstcount
A local host can access these registers using one of the following methods:
- Platform Designer (Standard) interconnect
- Custom logic
A local host can access the RapidIO registers from a Platform Designer (Standard) system. In this figure, a Nios II processor is part of the Platform Designer (Standard) system and is configured as an Avalon® -MM master that accesses the RapidIO IP core registers through the System Maintenance Avalon® -MM slave. Alternatively, you can implement custom logic to access the RapidIO registers.
A remote host can access the RapidIO registers by sending MAINTENANCE transactions targeted to this local RapidIO IP core. The Maintenance module processes MAINTENANCE transactions. If the transaction is a read or write, the operation is presented on the Maintenance Avalon® -MM master interface. This interface must be routed to the System Maintenance Avalon® -MM slave interface. This routing can be done with a Platform Designer (Standard) system shown by the routing to the Concentrator's system Maintenance Avalon® -MM slave in the previous figure. If you do not use a Platform Designer (Standard) system, you can create custom logic as shown below.