Visible to Intel only — GUID: ryl1490746614238
Ixiasoft
Visible to Intel only — GUID: ryl1490746614238
Ixiasoft
6.2.1. Capability Registers (CARs)
Field | Bits | Access | Function | Default |
---|---|---|---|---|
DEVICE_ID | [31:16] | RO | Hard-wired device identifier | 47 |
VENDOR_ID | [15:0] | RO | Hard-wired device vendor identifier | 47 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
DEVICE_REV | [31:0] | RO | Hard-wired device revision level | 47 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
ASSY_ID | [31:16] | RO | Hard-wired assembly identifier | 47 |
ASSY_VENDOR_ID | [15:0] | RO | Hard-wired assembly vendor identifier | 47 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
ASSY_REV | [31:16] | RO | Hard-wired assembly revision level | 47 |
EXT_FEATURE_PTR | [15:0] | RO | Hard-wired pointer to the first entry in the extended feature list. This pointer must be in the range of 16'h100 and 16'hFFFC. | 47 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
BRIDGE | [31] | RO | Processing element can bridge to another interface. | 47 |
MEMORY | [30] | RO | Processing element has physically addressable local address space and can be accessed as an endpoint through nonmaintenance operations. This local address space may be limited to local configuration registers, on-chip SRAM, or other device. | 47 |
PROCESSOR | [29] | RO | Processing element physically contains a local processor or similar device that executes code. A device that bridges to an interface that connects to a processor does not count. | 47 |
SWITCH | [28] | RO | Processing element can bridge to another external RapidIO interface—an internal port to a local endpoint does not count as a switch port. | 47 |
RSRV | [27:7] | RO | Reserved | 21'h0 |
RE_TRAN_SUP | [6] | RO | Processing element supports suppression of error recovery on packet CRC errors: 1'b0—The error recovery suppression option is not supported 1'b1—The error recovery suppression option is supported |
1'b0 |
CRF_SUPPORT | [5] | RO | Processing element supports the Critical Request Flow (CRF) indicator: 1'b0—Critical Request Flow is not supported 1'b1—Critical Request Flow is supported |
1'b0 |
LARGE_TRANSPORT | [4] | RO | Processing element supports common transport large systems: 1'b0—Processing element does not support common transport large systems (device ID width is 8 bits). 1'b1—Processing element supports common transport large systems (device ID width is 16 bits). The value of this field is determined by the device ID width you select in the RapidIO parameter editor. |
47 |
EXT_FEATURES | [3] | RO | Processing element has extended features list; the extended features pointer is valid. | 1'b1 |
EXT_ADDR_SPRT | [2:0] | RO | Indicates the number of address bits supported by the processing element, both as a source and target of an operation. All processing elements support a minimum 34-bit addresses: 3'b111—Processing element supports 66, 50, and 34-bit addresses 3'b101—Processing element supports 66 and 34-bit addresses 3'b011—Processing element supports 50 and 34-bit addresses 3'b001—Processing element supports 34-bit addresses |
3'b001 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:16] | RO | Reserved | 16'h0 |
PORT_TOTAL | [15:8] | RO | The total number of RapidIO ports on the processing element: 8'h0—Reserved 8'h1—1 port 8'h2—2 ports ... 8'hFF—255 ports |
47 |
PORT_NUMBER | [7:0] | RO | This is the port number from which the MAINTENANCE read operation accessed this register. Ports are numbered starting with 'h0. | 47 |
Field48 | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:16] | RO | Reserved | 16'h0 |
READ | [15] | RO | Processing element can support a read operation | 49 |
WRITE | [14] | RO | Processing element can support a write operation | 49 |
SWRITE | [13] | RO | Processing element can support a streaming-write operation | 49 |
NWRITE_R | [12] | RO | Processing element can support a write-with-response operation | 49 |
Data Message | [11] | RO | Processing element can support data message operation | 47 |
DOORBELL | [10] | RO | Processing element can support a DOORBELL operation | 50 |
ATM_COMP_SWP | [9] | RO | Processing element can support an ATOMIC compare-and-swap operation | 1'b0 |
ATM_TEST_SWP | [8] | RO | Processing element can support an ATOMIC test-and-swap operation | 1'b0 |
ATM_INC | [7] | RO | Processing element can support an ATOMIC increment operation | 1'b0 |
ATM_DEC | [6] | RO | Processing element can support an ATOMIC decrement operation | 1'b0 |
ATM_SET | [5] | RO | Processing element can support an ATOMIC set operation | 1'b0 |
ATM_CLEAR | [4] | RO | Processing element can support an ATOMIC clear operation | 1'b0 |
ATM_SWAP | [3] | RO | Processing element can support an ATOMIC swap operation | 1'b0 |
PORT_WRITE | [2] | RO | Processing element can support a port-write operation | 51 |
Implementation Defined | [1:0] | RO | Reserved for this implementation | 2'b00 |
Field52 | Bits | Access | Comment | Default |
---|---|---|---|---|
RSRV | [31:16] | RO | Reserved | 16'h0 |
READ | [15] | RO | Processing element can support a read operation | 53 |
WRITE | [14] | RO | Processing element can support a write operation | 53 |
SWRITE | [13] | RO | Processing element can support a streaming-write operation | 53 |
NWRITE_R | [12] | RO | Processing element can support a write-with-response operation | 53 |
Data Message | [11] | RO | Processing element can support data message operation | 47 |
DOORBELL | [10] | RO | Processing element can support a DOORBELL operation | 54 |
ATM_COMP_SWP | [9] | RO | Processing element can support an ATOMIC compare-and-swap operation | 1'b0 |
ATM_TEST_SWP | [8] | RO | Processing element can support an ATOMIC test-and-swap operation | 1'b0 |
ATM_INC | [7] | RO | Processing element can support an ATOMIC increment operation | 1'b0 |
ATM_DEC | [6] | RO | Processing element can support an ATOMIC decrement operation | 1'b0 |
ATM_SET | [5] | RO | Processing element can support an ATOMIC set operation | 1'b0 |
ATM_CLEAR | [4] | RO | Processing element can support an ATOMIC clear operation | 1'b0 |
ATM_SWAP | [3] | RO | Processing element can support an ATOMIC swap operation | 1'b0 |
PORT_WRITE | [2] | RO | Processing element can support a port-write operation | 55 |
Implementation Defined | [1:0] | RO | Reserved for this implementation | 2'b00 |
If one of the Logical layers supported by the RapidIO IP core is not selected in the MegaWizard Plug-In Manager, the corresponding bits in the Source and Destination Operations CARs are forced to zero. These bits cannot be set to one, even if the corresponding operations are supported by user logic attached to the Avalon® -ST pass-through interface.
If none of the Logical layers supported by the RapidIO IP core is selected, the corresponding bits in the Source and Destination Operations CAR are forced to zero. These bits cannot be set to one, even if the corresponding operations are supported by user logic attached to the Avalon® -ST pass-through interface.