Visible to Intel only — GUID: zjg1490746694772
Ixiasoft
Product Discontinuance Notification
1. About the RapidIO Intel FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. Platform Designer (Standard) Design Example
9. RapidIO Intel FPGA IP User Guide Archives
10. Document Revision History for the RapidIO Intel® FPGA IP User Guide
A. Initialization Sequence
B. Porting a RapidIO Design from the Previous Version of Software
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Generating IP Cores
2.3. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.4. RapidIO IP Core Testbench Files
2.5. Simulating IP Cores
2.6. Integrating Your IP Core in Your Design
2.7. Specifying Timing Constraints
2.8. Compiling the Full Design and Programming the FPGA
2.9. Instantiating Multiple RapidIO IP Cores
2.6.1. Calibration Clock
2.6.2. Dynamic Transceiver Reconfiguration Controller
2.6.3. Transceiver Settings
2.6.4. Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations
2.6.5. External Transceiver PLL
2.6.6. Transceiver PHY Reset Controller for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations
2.9.1. Clock and Signal Requirements for Arria® V, Cyclone® V, and Stratix® V Variations
2.9.2. Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations
2.9.3. Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances
2.9.4. Sourcing Multiple Tcl Scripts for Variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX
6.2.1. Capability Registers (CARs)
6.2.2. Command and Status Registers (CSRs)
6.2.3. Maintenance Interrupt Control Registers
6.2.4. Receive Maintenance Registers
6.2.5. Transmit Maintenance Registers
6.2.6. Transmit Port-Write Registers
6.2.7. Receive Port-Write Registers
6.2.8. Input/Output Master Address Mapping Registers
6.2.9. Input/Output Slave Mapping Registers
6.2.10. Input/Output Slave Interrupts
6.2.11. Transport Layer Feature Register
6.2.12. Error Management Registers
6.2.13. Doorbell Message Registers
7.1. Reset, Initialization, and Configuration
7.2. Maintenance Write and Read Transactions
7.3. SWRITE Transactions
7.4. NWRITE_R Transactions
7.5. NWRITE Transactions
7.6. NREAD Transactions
7.7. Doorbell Transactions
7.8. Doorbell and Write Transactions With Transaction Order Preservation
7.9. Port-Write Transactions
7.10. Transactions Across the Avalon® -ST Pass-Through Interface
Visible to Intel only — GUID: zjg1490746694772
Ixiasoft
4.6.2.6.1. Standard Error Management Registers
The following two standard defined error types can be declared by the I/O Avalon® -MM master module. The corresponding bits are then set and the required packet information is captured in the appropriate error management registers.
- Unsupported Transaction is declared when a request packet carries a transaction type that is not supported in the Destination Operations CAR, whether an ATOMIC transaction type, a reserved transaction type, or an implementation defined transaction type.
- Illegal Transaction Decode is declared when a request packet for a supported transaction is too short or if it contains illegal values in some of its fields such as in these examples:
- Request packet with priority = 3.
- NWRITE or NWRITE_R request packets without payload.
- NWRITE or NWRITE_R request packets with reserved wrsize and wdptr combination.
- NWRITE, NWRITE_R, SWRITE, or NREAD request packets for which the address does not match any enabled address mapping window.
- NREAD request packet with payload.
- NREAD request with rdsize that is not an integral number of transfers on all byte lanes. (The Avalon® -MM interface specification requires that all byte lanes be enabled for read transfers. Therefore, Read Avalon® -MM master modules do not have a byteenable signal).
- Payload size does not match the size indicated by the rdsize or wrsize and wdptr fields.
Related Information