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1. About the RapidIO Intel FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. Platform Designer (Standard) Design Example
9. RapidIO Intel FPGA IP User Guide Archives
10. Document Revision History for the RapidIO Intel® FPGA IP User Guide
A. Initialization Sequence
B. Porting a RapidIO Design from the Previous Version of Software
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Generating IP Cores
2.3. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.4. RapidIO IP Core Testbench Files
2.5. Simulating IP Cores
2.6. Integrating Your IP Core in Your Design
2.7. Specifying Timing Constraints
2.8. Compiling the Full Design and Programming the FPGA
2.9. Instantiating Multiple RapidIO IP Cores
2.6.1. Calibration Clock
2.6.2. Dynamic Transceiver Reconfiguration Controller
2.6.3. Transceiver Settings
2.6.4. Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations
2.6.5. External Transceiver PLL
2.6.6. Transceiver PHY Reset Controller for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations
2.9.1. Clock and Signal Requirements for Arria® V, Cyclone® V, and Stratix® V Variations
2.9.2. Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations
2.9.3. Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances
2.9.4. Sourcing Multiple Tcl Scripts for Variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX
6.2.1. Capability Registers (CARs)
6.2.2. Command and Status Registers (CSRs)
6.2.3. Maintenance Interrupt Control Registers
6.2.4. Receive Maintenance Registers
6.2.5. Transmit Maintenance Registers
6.2.6. Transmit Port-Write Registers
6.2.7. Receive Port-Write Registers
6.2.8. Input/Output Master Address Mapping Registers
6.2.9. Input/Output Slave Mapping Registers
6.2.10. Input/Output Slave Interrupts
6.2.11. Transport Layer Feature Register
6.2.12. Error Management Registers
6.2.13. Doorbell Message Registers
7.1. Reset, Initialization, and Configuration
7.2. Maintenance Write and Read Transactions
7.3. SWRITE Transactions
7.4. NWRITE_R Transactions
7.5. NWRITE Transactions
7.6. NREAD Transactions
7.7. Doorbell Transactions
7.8. Doorbell and Write Transactions With Transaction Order Preservation
7.9. Port-Write Transactions
7.10. Transactions Across the Avalon® -ST Pass-Through Interface
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6.2.8. Input/Output Master Address Mapping Registers
When the IP core receives an NREAD, NWRITE, NWRITE_R, or SWRITE request packet, the RapidIO address has to be translated into a local Avalon® -MM address. The translation involves the base, mask, and offset registers. There are up to 16 register sets, one for each address mapping window. The 16 possible register address offsets are shown below the table titles.
Field | Bits | Access | Function | Default |
---|---|---|---|---|
BASE | [31:3] | RW | Start of the RapidIO address window to be mapped. The three least significant bits of the 34-bit base are assumed to be zeros. | 29'h0 |
RSRV | [2] | RO | Reserved | 1'b0 |
XAMB | [1:0] | RW | Extended Address: two most significant bits of the 34-bit base. | 2'h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
MASK | [31:3] | RW | Bits 31 to 3 of the mask for the address mapping window. The three least significant bits of the 34-bit mask are assumed to be zeros. | 29'h0 |
WEN | [2] | RW | Window enable. Set to one to enable the corresponding window. | 1'b0 |
XAMM | [1:0] | RW | Extended Address: two most significant bits of the 34-bit mask. | 2’b0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
OFFSET | [31:3] | RW | Starting offset into the Avalon® -MM address space. The three least significant bits of the 32-bit offset are assumed to be zero. | 29'h0 |
RSRV | [2:0] | RO | Reserved | 3'h0 |
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