Visible to Intel only — GUID: beq1490746701749
Ixiasoft
Visible to Intel only — GUID: beq1490746701749
Ixiasoft
6.1. Physical Layer Registers
The offset values are defined by the RapidIO standard.
Address | Name | Description |
---|---|---|
0x100 | PHEAD0 | LP-Serial Register Block Header |
0x104 | PHEAD1 | Reserved register |
0x120 | PLTCTRL | Port Link Time-out Control CSR |
0x124 | PRTCTRL | Port Response Time-out Control CSR |
0x13C | PGCTRL | Port General Control CSR |
0x158 | ERRSTAT | Port 0 Error and Status CSR |
0x15C | PCTRL0 | Port 0 Control CSR |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
EF_PTR | [31:16] | RO | Hard-wired pointer to the next block in the data structure, if one exists. The value is set from the ef_ptr input port. | ef_ptr |
EF_ID | [15:0] | RO | Hard-wired extended features ID. | 16'h0001 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:0] | UR0 | Reserved | 32’h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
VALUE | [31:8] | RW | Time-out interval value for link-layer event pairs such as the time interval between sending a packet and receiving the corresponding acknowledge control symbol, or between sending a link-request and receiving the corresponding link-response. The duration of the link-response time-out is approximately equal to 4.5 seconds multiplied by the contents of this field, divided by (224 - 1). Note: Avoid time-out values less than 0x000010 because they may not be reliable. | 24'hFF_FFFF |
RSRV | [7:0] | UR0 | Reserved | 8’h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
VALUE | [31:8] | RW | Time-out internal value.
|
24'hFF_FFFF |
RSRV | [7:0] | UR0 | Reserved | 8'h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
HOST | [31] | RW | A host device is a device that is responsible for system exploration, initialization, and maintenance. Host devices typically initialize agent or slave devices. 'b0 - agent or slave device 'b1 - host device |
1'b0 |
ENA | [30] | RW | The Master Enable bit controls whether or not a device is allowed to issue requests to the system. If Master Enable is not set, the device may only respond to requests. 'b0 - The processing element cannot issue requests 'b1 - The processing element can issue requests Variations that use only the Physical layer ignore this bit. |
1'b0 |
DISCOVER | [29] | RW | This device has been located by the processing element responsible for system configuration. 'b0 - The device has not been previously discovered 'b1 - The device has been discovered by another processing element |
1'b0 |
RSRV | [28:0] | RO | Reserved | 29'b0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:29] | RO | Reserved | 3'b0 |
INBOUND_ACKID | [28:24] | RO | Next expected packet ackID. | 5’b0 |
RSRV | [23:13] | RO | Reserved | 11’b0 |
OUTSTANDING_ ACKID | [12:8] | RO | Next expected acknowledge control-symbol ackID. | 5'b0 |
RSRV | [7:5] | RO | Reserved | 3'b0 |
OUTBOUND_ACKID | [4:0] | RO | Next transmitted packet ackID. | 5'b0 |
Field45 | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:21] | RO | Reserved | 11'b0 |
OUT_RTY_ENC | [20] | RW1C | Output port has encountered a retry condition. In all cases, this condition is caused by the port receiving a packet-retry control symbol. This bit is set if the OUT_RTY_STOP bit is set. | 1'b0 |
OUT_RETRIED | [19] | RO | Output port has received a packet-retry control symbol and cannot make forward progress. This bit is cleared when a packet-accepted or packet-not-accepted control symbol is received. | 1'b0 |
OUT_RTY_STOP | [18] | RO | Output port has been stopped due to a retry and is trying to recover. When a port receives a packet_retry control symbol, it enters the Output Retry Stopped state. In this state, the port transmits a restart-from-retry control symbol to its link partner. The link partner exits the Input Retry Stopped state and normal operation resumes. The port exits the Output Retry Stopped state. | 1'b0 |
OUT_ERR_ENC | [17] | RW1C | Output port has encountered a transmission error and has possibly recovered from it. This bit is set when the OUT_ERR_STOP bit is set. | 1'b0 |
OUT_ERR_STOP | [16] | RO | Output port has been stopped due to a transmission error and is trying to recover. The output port is in the Output Error Stopped state. The port enters into this state when it receives a packet-not-accepted control symbol. To exit from this state, the port issues an input-status link-request/input-status (restart-from-error) control symbol. The port waits for the link-response control symbol and exits the Output Error Stopped state. | 1'b0 |
RSRV | [15:11] | RO | Reserved | 5'b0 |
IN_RTY_STOP | [10] | RO | Input port is stopped due to a retry. When the receiver issues a packet-retry control symbol to its link partner, it enters the Input Retry Stopped state. The receiver issues a packet-retry when sufficient buffer space is not available to accept the packet for that specific priority. The receiver continues in the Input Retry Stopped state until it receives a restart-from-retry control symbol. | 1'b0 |
IN_ERR_ENC | [9] | RW1C | Input port has encountered a transmission error. This bit is set if the IN_ERR_STOP bit is set. | 1'b0 |
IN_ERR_STOP | [8] | RO | Input port is stopped due to a transmission error. The port is in the Input Error Stop state. The following conditions cause the input port to transition to this state:
|
1'b0 |
RSRV | [7:5] | RO | Reserved | 3'h0 |
PWRITE_PEND | [4] | RO | This register is not implemented and is reserved. It is always set to zero. | 1'b0 |
RSRV | [3] | RO | Reserved | 1'b0 |
PORT_ERR | [2] | RW1C | This bit is set if the input port error recovery state machine encounters an unrecoverable error or the output port error recovery state machine enters the fatal_error state. The input port error recovery state machine encounters an unrecoverable error if it times out while waiting for a link-request after sending a packet-not-accepted control symbol. The output port error recovery state machine enters the fatal_error state if the following sequence of events occurs: The output port error recovery state machine enters the stop_output state when it receives a packet-not-accepted control symbol. In response, it sends the input-status link-request/input-status (restart-from-error) control symbol. One of the following events occurs in response to the link-request control symbol: If the link-response is received but the ackID is outside of the outstanding ackID set, or the port_status value is Error, then the output port error recovery state machine enters the fatal_error state. If the port times out before receiving link-response, and the number of times this time-out event has occurred reaches the number you set in the RapidIO parameter editor as the value for Link-request attempts, then the output port error recovery state machine enters the fatal_error state. When the PORT_ERR bit is set, the RapidIO IP core performs an internal soft reset sequence, as described in “Fatal Errors”. The port_error output signal mirrors this register bit. |
1'b0 |
PORT_OK | [1] | RO | Input and output ports are initialized and can communicate with the adjacent device. This bit is asserted when port_initialized is asserted and the following conditions exist:
|
1'b0 |
PORT_UNINIT | [0] | RO | Input and output ports are not initialized and are in training mode. This bit is the negation of the PORT_OK bit. | 1'b1 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
PORT_WIDTH | [31:30] | RO | Hardware width of the port: 'b00—Single-lane port. 'b10—Two-lane port. 'b01—Four-lane port. ''b11—Reserved. |
2'b00 (for 1x variations), 2'b10 (for 2x variations), 2'b01 (for 4x variations)46 |
INIT_WIDTH | [29:27] | RO | Width of the ports after being initialized: 'b000—Single lane port, lane 0. 'b001—Single lane port, redundancy lane (lane 1 for 2x variations and lane 2 for 4x variations). 'b010—Four-lane port. 'b011—Two-lane port. ‘b100 – 'b111—Reserved. |
3'b000 (for 1x variations), 3'b011 (for 2x variations), 3'b010 (for 4x variations) |
PWIDTH_OVRIDE | [26:24] | UR0 | Soft port configuration to override the hardware size: 'b000—No override. 'b001—Reserved. 'b010—Force single lane, lane 0. 'b011—Force single lane, redundancy lane. 'b100–'b111—Reserved. |
3'b000 |
PORT_DIS | [23] | RW | Port disable: 'b0—Port receivers/drivers are enabled. 'b1—Port receivers are disabled, causing the drivers to send out idles.
|
1'b0 |
OUT_PENA | [22] | RW | Output port transmit enable: 'b0—Port is stopped and not enabled to issue any packets except to route or respond to I/O logical MAINTENANCE packets, depending upon the functionality of the processing element. Control symbols are not affected and are sent normally. 'b1—Port is enabled to issue packets. |
1'b1 |
IN_PENA | [21] | RW | Input port receive enable: 'b0—Port is stopped and only enabled to respond I/O Logical MAINTENANCE requests. Other requests return packet-not-accepted control symbols to force an error condition to be signaled by the sending device 'b1—Port is enabled to respond to any packet |
1'b1 |
ERR_CHK_DIS | [20] | RW | This bit controls all RapidIO transmission error checking: 'b0—Error checking and recovery is enabled 'b1—Error checking and recovery is disabled Device behavior when error checking and recovery is disabled and an error condition occurs is undefined. |
1'b0 |
Multicast-event Participant | [19] | RW | Send incoming Multicast-event control symbols to this port (multiple port devices only). | 1'b0 |
RSRV | [18] | RO | Reserved | 1'b0 |
Enumeration Boundary | [17] | RO | This feature is not supported. | 1'b0 |
RSRV | [16:12] | RO | Reserved | 5'b0 |
Re-transmit Suppression Mask | [11:4] | RO | This feature is not supported. | 8’b0 |
RSRV | [3:1] | RO | Reserved | 3’b0 |
PORT_TYPE | [0] | RO | This bit indicates the port type, parallel or serial. 'b0—Parallel port 'b1—Serial port |
1'b1 |