RapidIO Intel FPGA IP User Guide

Download PDF
ID 683884
Date 9/15/2021
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the RapidIO Intel FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Signals 6. Software Interface 7. Testbench 8. Platform Designer (Standard) Design Example 9. RapidIO Intel FPGA IP User Guide Archives 10. Document Revision History for the RapidIO Intel® FPGA IP User Guide A. Initialization Sequence B. Porting a RapidIO Design from the Previous Version of Software
1. About the RapidIO Intel FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grades 1.6. Release Information
1.1. Features x
1.1.1. Supported Transactions
1.3. IP Core Verification x
1.3.1. Simulation Testing 1.3.2. Hardware Testing 1.3.3. Interoperability Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generating IP Cores 2.3. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition) 2.4. RapidIO IP Core Testbench Files 2.5. Simulating IP Cores 2.6. Integrating Your IP Core in Your Design 2.7. Specifying Timing Constraints 2.8. Compiling the Full Design and Programming the FPGA 2.9. Instantiating Multiple RapidIO IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Generating IP Cores x
2.2.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.5. Simulating IP Cores x
2.5.1. Simulating the Testbench with the ModelSim Simulator 2.5.2. Simulating the Testbench with the VCS Simulator 2.5.3. Simulating the Testbench with the Xcelium Simulator
2.6. Integrating Your IP Core in Your Design x
2.6.1. Calibration Clock 2.6.2. Dynamic Transceiver Reconfiguration Controller 2.6.3. Transceiver Settings 2.6.4. Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations 2.6.5. External Transceiver PLL 2.6.6. Transceiver PHY Reset Controller for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations
2.9. Instantiating Multiple RapidIO IP Cores x
2.9.1. Clock and Signal Requirements for Arria® V, Cyclone® V, and Stratix® V Variations 2.9.2. Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations 2.9.3. Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances 2.9.4. Sourcing Multiple Tcl Scripts for Variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX
3. Parameter Settings x
3.1. Physical Layer Settings 3.2. Transport and Maintenance Settings 3.3. I/O and Doorbell Settings 3.4. Capability Registers Settings
3.1. Physical Layer Settings x
3.1.1. Device Options 3.1.2. Data Settings 3.1.3. Receive Priority Retry Thresholds 3.1.4. Transceiver Settings
3.2. Transport and Maintenance Settings x
3.2.1. Transport Layer 3.2.2. Input/Output Maintenance Logical Layer Module 3.2.3. Port Write
3.3. I/O and Doorbell Settings x
3.3.1. I/O Logical Layer Interfaces 3.3.2. I/O Slave Address Width 3.3.3. I/O Read and Write Order Preservation 3.3.4. Avalon® -MM Master 3.3.5. Avalon® -MM Slave 3.3.6. Doorbell Slave
3.4. Capability Registers Settings x
3.4.1. Device Registers 3.4.2. Assembly Registers 3.4.3. Processing Element Features 3.4.4. Switch Support 3.4.5. Data Messages
4. Functional Description x
4.1. Interfaces 4.2. Clocking and Reset Structure 4.3. Physical Layer 4.4. Transport Layer 4.5. Logical Layer Modules 4.6. Error Detection and Management
4.1. Interfaces x
4.1.1. RapidIO Interface 4.1.2. Avalon® Memory Mapped ( Avalon® -MM) Master and Slave Interfaces 4.1.3. Avalon® Streaming ( Avalon® -ST) Interface
4.1.2. Avalon® Memory Mapped ( Avalon® -MM) Master and Slave Interfaces x
4.1.2.1. Avalon® -MM Interface Widths in the RapidIO IP Core 4.1.2.2. Avalon® -MM Interface Byte Ordering
4.2. Clocking and Reset Structure x
4.2.1. RapidIO IP Core Clocking 4.2.2. Reset for RapidIO IP Cores
4.2.1. RapidIO IP Core Clocking x
4.2.1.1. Avalon® System Clock 4.2.1.2. Reference Clock 4.2.1.3. Other Input Clocks 4.2.1.4. Clock Domains 4.2.1.5. Baud Rates and Clock Frequencies
4.2.2. Reset for RapidIO IP Cores x
4.2.2.1. General RapidIO Reset Signal Requirements 4.2.2.2. Reset Controller 4.2.2.3. Reset Requirements for Arria® V, Cyclone® V, and Stratix® V Variations 4.2.2.4. Reset Requirements for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations 4.2.2.5. RapidIO IP Core Reset Behavior
4.3. Physical Layer x
4.3.1. Features 4.3.2. Physical Layer Architecture 4.3.3. Low-level Interface Receiver 4.3.4. Low-Level Interface Transmitter 4.3.5. Protocol and Flow Control Engine 4.3.6. Physical Layer Receive Buffer 4.3.7. Physical Layer Transmit Buffer
4.3.3. Low-level Interface Receiver x
4.3.3.1. Receiver Transceiver 4.3.3.2. CRC Checking and Removal
4.3.4. Low-Level Interface Transmitter x
4.3.4.1. Transmitter Transceiver
4.3.6. Physical Layer Receive Buffer x
4.3.6.1. Error Conditions that Flush the Receive Buffer 4.3.6.2. Error Conditions Flagged for the Transport Layer 4.3.6.3. Receive Priority Threshold Values
4.3.7. Physical Layer Transmit Buffer x
4.3.7.1. Transmit and Retransmit Queues 4.3.7.2. Error Conditions that Flush the Transmit Buffer 4.3.7.3. Forced Compensation Sequence Insertion
4.4. Transport Layer x
4.4.1. Receiver 4.4.2. Transaction ID Ranges 4.4.3. Transmitter
4.5. Logical Layer Modules x
4.5.1. Concentrator Register Module 4.5.2. Maintenance Module 4.5.3. Input/Output Logical Layer Modules 4.5.4. Doorbell Module 4.5.5. Avalon® -ST Pass-Through Interface
4.5.2. Maintenance Module x
4.5.2.1. Maintenance Register 4.5.2.2. Maintenance Slave Processor 4.5.2.3. Maintenance Master Processor 4.5.2.4. Port-Write Processor 4.5.2.5. Maintenance Module Error Handling
4.5.2.4. Port-Write Processor x
4.5.2.4.1. Port-Write Transmission 4.5.2.4.2. Port-Write Reception
4.5.3. Input/Output Logical Layer Modules x
4.5.3.1. Input/Output Avalon® -MM Master Module 4.5.3.2. Input/Output Avalon® -MM Master Module Timing Diagrams 4.5.3.3. Input/Output Avalon® -MM Slave Module 4.5.3.4. Avalon® -MM Burstcount and Byteenable Encoding in RapidIO Packets 4.5.3.5. Input/Output Avalon® -MM Slave Module Timing Diagrams
4.5.3.1. Input/Output Avalon® -MM Master Module x
4.5.3.1.1. Input/Output Avalon® -MM Master Address Mapping Windows
4.5.3.3. Input/Output Avalon® -MM Slave Module x
4.5.3.3.1. Keeping Track of I/O Write Transactions 4.5.3.3.2. Input/Output Avalon® -MM Slave Address Mapping Windows 4.5.3.3.3. Input/Output Slave Translation Window Example 4.5.3.3.4. Translation Window 0 4.5.3.3.5. Translation Window 1 4.5.3.3.6. Translation Window 2
4.5.4. Doorbell Module x
4.5.4.1. Doorbell Module Block Diagram 4.5.4.2. Preserving Transaction Order 4.5.4.3. Doorbell Message Generation 4.5.4.4. Doorbell Message Reception
4.5.5. Avalon® -ST Pass-Through Interface x
4.5.5.1. Pass-Through Interface Examples
4.6. Error Detection and Management x
4.6.1. Physical Layer Error Management 4.6.2. Logical Layer Error Management 4.6.3. Avalon® -ST Pass-Through Interface
4.6.1. Physical Layer Error Management x
4.6.1.1. Protocol Violations 4.6.1.2. Fatal Errors
4.6.2. Logical Layer Error Management x
4.6.2.1. Maintenance Avalon® -MM Slave 4.6.2.2. Maintenance Avalon® -MM Master 4.6.2.3. Port-Write Reception Module 4.6.2.4. Port-Write Transmission Module 4.6.2.5. Input/Output Avalon® -MM Slave 4.6.2.6. Input/Output Avalon® -MM Master
4.6.2.1. Maintenance Avalon® -MM Slave x
4.6.2.1.1. Standard Error Management Registers 4.6.2.1.2. Registers in the Implementation Defined Space 4.6.2.1.3. Maintenance Avalon® -MM Slave Interface's Error Indication Signal
4.6.2.5. Input/Output Avalon® -MM Slave x
4.6.2.5.1. Standard Error Management Registers 4.6.2.5.2. Registers in the Implementation Defined Space 4.6.2.5.3. The Avalon® -MM Slave Interface's Error Indication Signal
4.6.2.6. Input/Output Avalon® -MM Master x
4.6.2.6.1. Standard Error Management Registers 4.6.2.6.2. Response Packets with ERROR Status
5. Signals x
5.1. Physical Layer Signals 5.2. Transport and Logical Layer Signals
5.1. Physical Layer Signals x
5.1.1. Status Packet and Error Monitoring Signals 5.1.2. Multicast Event Signals 5.1.3. Receive Priority Retry Threshold-Related Signals 5.1.4. Physical Layer Buffer Status Signals 5.1.5. Transceiver Signals 5.1.6. Register-Related Signals
5.2. Transport and Logical Layer Signals x
5.2.1. Avalon® -MM Interface Signals 5.2.2. Avalon® -ST Pass-Through Interface Signals 5.2.3. Error Management Extension Signals 5.2.4. Packet and Error Monitoring Signal for the Transport Layer
6. Software Interface x
6.1. Physical Layer Registers 6.2. Transport and Logical Layer Registers
6.2. Transport and Logical Layer Registers x
6.2.1. Capability Registers (CARs) 6.2.2. Command and Status Registers (CSRs) 6.2.3. Maintenance Interrupt Control Registers 6.2.4. Receive Maintenance Registers 6.2.5. Transmit Maintenance Registers 6.2.6. Transmit Port-Write Registers 6.2.7. Receive Port-Write Registers 6.2.8. Input/Output Master Address Mapping Registers 6.2.9. Input/Output Slave Mapping Registers 6.2.10. Input/Output Slave Interrupts 6.2.11. Transport Layer Feature Register 6.2.12. Error Management Registers 6.2.13. Doorbell Message Registers
7. Testbench x
7.1. Reset, Initialization, and Configuration 7.2. Maintenance Write and Read Transactions 7.3. SWRITE Transactions 7.4. NWRITE_R Transactions 7.5. NWRITE Transactions 7.6. NREAD Transactions 7.7. Doorbell Transactions 7.8. Doorbell and Write Transactions With Transaction Order Preservation 7.9. Port-Write Transactions 7.10. Transactions Across the Avalon® -ST Pass-Through Interface
8. Platform Designer (Standard) Design Example x
8.1. Creating a New Intel® Quartus® Prime Project 8.2. Running Platform Designer (Standard) 8.3. Simulating the System
8.2. Running Platform Designer (Standard) x
8.2.1. Adding and Parameterizing the RapidIO Component 8.2.2. Adding and Connecting Other System Components 8.2.3. Connecting Clocks and the System Components 8.2.4. Generating the System
8.2.2. Adding and Connecting Other System Components x
8.2.2.1. Adding the Master Maintenance BFM 8.2.2.2. Adding the Master I/O BFM 8.2.2.3. Adding the On-Chip Memory
8.2.3. Connecting Clocks and the System Components x
8.2.3.1. Connecting Unconnected Clocks 8.2.3.2. Connecting System Components 8.2.3.3. Assigning Addresses and Setting the Clock Frequency
B. Porting a RapidIO Design from the Previous Version of Software x
B.1. Upgrading a RapidIO Design Without Changing Device Family B.2. Upgrading a RapidIO Design to the Intel® Arria® 10 and Intel® Cyclone® 10 GX Device Families
Product Discontinuance Notification
1. About the RapidIO Intel FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. Platform Designer (Standard) Design Example
9. RapidIO Intel FPGA IP User Guide Archives
10. Document Revision History for the RapidIO Intel® FPGA IP User Guide
A. Initialization Sequence
B. Porting a RapidIO Design from the Previous Version of Software

10. Document Revision History for the RapidIO Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.09.15 20.3 19.2.0 Updated Table: RapidIO Release Information for clarity. The RapidIO Intel® FPGA IP is no longer supported in Intel® Quartus® Prime Pro Edition software version 20.3 and later, and Intel® Quartus® Prime Standard Edition software version 18.1 and later.
2020.09.28 20.3 19.2.0
  • Added the Product Discontinuance Notice.
  • Added IP version information.
2018.08.09 18.0 18.0
  • Added txclk and rxclk frequencies into Clock Frequencies for 4x RapidIO IP Core Variations.
  • Added support for Intel® Cyclone® 10 GX devices.
  • Added Xcelium* simulator support.
  • Renamed the document as RapidIO Intel FPGA IP User Guide.
  • Added txclk, rxclk values in Clock Frequencies for 1x and 2x RapidIO IP Core Variations table.
Date Changes
November 2017
  • Updated for Intel® Quartus® Prime 17.1 release.
  • Updated the resource utilization metrics for all device variations in Performance and Resource Utilization section.
  • Modified steps to generate the Platform Designer (Standard) system in Generating the System section.
  • Updated command in Simulating the System section to simulate system with the sample Verilog HDL testbench in ModelSim software.
May 2017
  • Changed the document title from "RapidIO MegaCore Function User Guide" to "RapidIO IP Core User Guide".
  • Changed the document part number from UG-MC_RIOPHY-4.1 to UG-20078 .
  • Updated device support level for Arria® V (GX, GT ,GZ, SX, and ST), Intel® Arria® 10, Cyclone® V (GX, GT, SX, and ST), and Stratix® V device family in Table: Device Family Support.
  • Updated the resource utilization metrics for all device variations in Performance and Resource Utilization.
  • Updated Getting Started chapter for the Intel® Quartus® Prime 17.0 software.
  • Added new section RapidIO IP Core Testbench Files.
  • Made following changes to Simulating the Testbench with the ModelSim Simulator:
    • Updated steps to simulate the testbench.
    • Updated testbench script location for all device variations.
    • Updated commands for all device variations.
    • Corrected TOP_LEVEL_NAME for all device variations.
  • Updated testbench script location for all device variations in Simulating the Testbench with the VCS Simulator.
  • Added new section Transceiver PHY Reset Controller for Intel® Arria® 10 Variations.
  • Made following changes to External Transceiver PLL:
    • Clarified that an fPLL can also implement the required external transceiver PLL in an IP core that targets an Intel® Arria® 10 device.
    • Updated the location of the HDL code for an ATX PLL.
    • Added note to clarify the file name of ATX PLL HDL code for Intel® Arria® 10 devices.
  • Updated the value of rxgxbclk for Arria® V and Cyclone® V devices in Table: Clock Frequencies for 1x and 2x RapidIO IP Core Variations.
  • Clarified the value of default clock frequency for all device variations in Baud Rates and Clock Frequencies.
  • Added information about required parameter value for the Transceiver PHY Reset Controller that connects to the RapidIO IP core in Reset Requirements for Intel® Arria® 10 Variations.
  • Added new signals:
    • input_enable
    • output_enable
    • no_sync_indicator
  • Added information in RapidIO IP Core Clocking to confirm that RapidIO IP core can handle a difference of ±200 ppm between the rxclk and txclk clocks.
  • Added new parameter Packet-Not-Accepted to Link Request timeout in Physical Layer Settings.
  • Implemented Intel® Rebranding.
August 2014
  • Added support for Intel® Arria® 10 devices:

    New parameter Enable transceiver dynamic reconfiguration allows you to hide or make visible the Intel® Arria® 10 Native PHY IP core dynamic reconfiguration interface, an Avalon® -MM interface for programming the hard registers in the Intel® Arria® 10 transceiver.

    New requirement to include TX PLL IP core in the Intel® Arria® 10 design. RapidIO IP core has new individual transceiver channel clock signals tx_bonded_clocks_chN to connect to an ATX PLL to support PLL sharing across the transceiver block.

    New requirement to include a reset controller in the Intel® Arria® 10 design. RapidIO IP core has new transceiver reset signals tx_analogreset, rx_analogreset, tx_digitalreset, and rx_digitalreset to connect to the reset controller.

    Only certain IP core variations support Intel® Arria® 10 devices. Refer to Chapter: Parameter Settings or Upgrading a RapidIO Design to the Intel® Arria® 10 Device Family for information about the supported and unsupported IP core variations.

  • Updated migration information for the v14.0 Intel® Arria® 10 Edition software release in Appendix: Porting a RapidIO Design from the Previous Version of the Software.
June 2014
  • Removed device support, resource utilization numbers, and speed grade information for the following device families that the Quartus II software v13.1 and later no longer supports: Arria GX, Cyclone II, Stratix II, and Stratix II GX device families.
  • Removed device support for the following HardCopy device families: HardCopy II, HardCopy III, HardCopy IV E, and HardCopy IV GX device families. This device support was removed in the 13.1 release.
  • Removed device support, resource utilization numbers, and speed grade information for the following device families that the Quartus II software v14.0 and later no longer supports: Cyclone III, Cyclone III LS, and Stratix III device families.
  • Renamed and reordered resource utilization tables in Performance and Resource Utilization section.
  • Replaced “Serial RapidIO” with “RapidIO”. The RapidIO IP core supports only the Serial RapidIO specification, since before the Quartus II software release 8.0 in 2008.
  • Modified Chapter: Getting Started to describe the new Quartus II software v14.0 IP design flow.
  • Updated migration information for the v14.0 software release in Appendix: Porting a RapidIO Design from the Previous Version of the Software.

  • Removed support for Physical-layer only variations. The RapidIO IP core no longer supports Physical-layer only variations.

    Removed information about clocking, reset, and testbench for Physical-layer only variations.

    Removed the PHY Maintenance Avalon-MM slave interface signals (phy_mnt_s_clk, phy_mnt_s_chipselect, phy_mnt_s_waitrequest, phy_mnt_s_read, phy_mnt_s_write, phy_mnt_s_addresss, phy_mnt_s_writedata, phy_mnt_s_readdata). This interface is no longer a top-level interface. In variations with a Transport layer, software accesses the Physical layer registers through the system maintenance Avalon-MM slave interface instead.

    Removed the Calculating Resource Utilization for Modular Configurations appendix.

  • Corrected the description of the atxwlevel, atxovf, and arxwlevel Physical-layer buffer status output signals to indicate they are available. These signals were previously described incorrectly as being available only in Physical-layer-only variations.
  • Added section Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances. This section describes an additional requirement for ensuring a design with multiple RapidIO IP core instances functions correctly.
  • Added new section Avalon® -MM Interface Widths in the RapidIO IP Core.
  • Clarified that sys_mnt_s_address, mnt_s_address, and drbell_s_address are word addresses and not byte addresses. They each address a four-byte (32-bit) word. Modified Maintenance TX address window translation calculation accordingly in Maintenance Module.
  • Corrected the width of mnt_s_address to 24 bits and in the Maintenance TX address window translation calculation description in Maintenance Module.
  • Clarified that io_s_wr_address and io_s_rd_address are word addresses (and not byte addresses) in RapidIO 1x variations, and are double-word addresses in 2x and 4x variations. Corrected header and note in to specify that the bit that provides the wdptr information is bit [0] rather than bit [2]. Corrected address window translation calculation and examples accordingly in Input/Output Avalon® -MM Slave Module.
  • Updated parameter descriptions in Chapter: Parameter Settings.

    Updated capitalization and minor changes in parameter names.

    Transceiver selection is no longer modifiable. The remaining supported device families do not support an external transceiver option.

    Removed the Transceiver Configuration option.

    Removed Enable Transport Layer parameter. The RapidIO IP core no longer supports Physical-layer only variations: all variations have a Transport layer.

    Removed EDA Settings and Summary sections. These tabs no longer exist in the RapidIO parameter editor in the new Quartus II software v14.0 IP design flow.

  • Updated migration information in Appendix: Porting a RapidIO Design from the Previous Version of the Software and removed information about porting from SOPC Builder.
  • Removed dedicated appendix and other information about the XGMII external transceiver interfaces. This interface is not available for any of the current supported device families.
  • Removed some information about signals exported by Platform Designer (Standard) from Chapter: Signals, and redundant information about Platform Designer (Standard) renaming capability. Platform Designer (Standard) is documented in the Quartus Prime Standard Edition Handbook.
  • Corrected direction of rxgxbclk output clock signal in Transceiver Signals.
May 2013
  • Removed SOPC Builder design flow, which is no longer available.
May 2013
  • Added 2x mode for variations that target any Arria® V, Cyclone® V, or Stratix® V device, including modification of the descriptions of the PORT_WIDTH and INIT_WIDTH fields in Port 0 Control CSR in to include 2x mode options. This feature is available in the Quartus II software 13.0 release and later.
  • Added support for Arria® V GZ, Arria® V SX, Arria® V ST, Cyclone® V SX, and Cyclone® V ST devices. This support is available in the Quartus II software 12.1 release and later.
  • Updated resource utilization information for Arria® V, Cyclone® V, and Stratix® V devices.
  • Updated Cyclone® V GT and Stratix® V speed grade support information.
  • Corrected entries in , Write Request Size Encoding (32-bit datapath) and, Read Request Size Encoding (64-bit datapath).
  • Corrected and enhanced information about gen_rx_empty output signal .
May 2012
  • Added support for Cyclone® V GT ×1 variation at 5.0 Gbaud.
  • Updated speed grade support for Arria® V, Stratix IV GX, and Stratix® V devices.
  • Moved Modular Configurations section from Chapter 1, About This MegaCore Function to new Appendix D, Calculating Resource Utilization for Modular Configurations.
  • Clarified additional constraints on deassertion of reset_n and phy_mgmt_clk_reset.
November 2011
  • Added support for Arria® V and Cyclone® V devices. Variations that target one of these two device families configure the transceiver with the Custom PHY IP core.
  • Added Chapter: Platform Designer (Standard) Design Example.
  • Enhanced description of arxmty signal.
  • Updated simulation sections in Chapter: Getting Started.
May 2011
  • Upgraded to final support for Arria II GZ, Cyclone III LS, and Cyclone IV GX devices.
  • Upgraded to HardCopy Compilation support for HardCopy III, HardCopy IV E, and HardCopy IV GX devices.
  • Added preliminary support for Stratix® V devices.
  • Added support for Custom PHY IP core in variations that target a Stratix® V device.
December 2010
  • Added beta support for Platform Designer (Standard) system integration tool.
  • Added read-only version of Port 0 Local AckID CSR.
July 2010
  • Added preliminary support for Cyclone IV GX devices.
  • Added support for configurable number of link-request attempts to be sent before fatal error, after time-out on link-response.
  • Added support for order preservation between read and write requests that come in on the Avalon® -MM interface.
  • Removed support for Stratix GX devices.
November 2009
  • Added preliminary support for Cyclone III LS and HardCopy IV GX devices.
  • Added support for 5.0 Gbaud data rate.
  • Added support for order preservation between I/O write requests and DOORBELL requests.
  • Added NWRITE_R completion indication.
  • Added post-reset ackID synchronization.
  • Added transceiver configuration using full transceiver parameter editor.
March 2009
  • Corrected to preliminary support for HardCopy II devices.
  • Clarified the RapidIO IP core uses the transceiver bonded mode where relevant.
  • Updated Table 4–17.
February 2009
  • Added preliminary support for Arria II GX devices.
  • Added preliminary support for HardCopy III and HardCopy IV E devices.
  • Added support for outgoing multicast-event symbol generation.
  • Added support for 16-bit device ID.
  • Added Appendix C, Porting a RapidIO Design from the Previous Version of the Software.
November 2008
  • Added full support for Stratix III devices.
  • Added support for incoming multicast transactions.
  • Added GUI and register support to enable or disable destination ID checking.
  • Added GUI support to set transceiver starting channel number.
  • Added requirement to configure a dynamic reconfiguration block with Stratix IV transceivers, to enable offset cancellation.
  • Updated Figure 4–6 and Figure 7–2.
May 2008
  • Added Arria GX device support for 1x mode 3.125 GBaud variation.
  • Added Stratix IV device support.
  • Added GUI support to set VCCH and reference clock frequency.
  • Simplified Physical layer description in Functional Description chapter.
  • Updated the performance information.
October 2007
  • Added Avalon® -ST pass-through interface to SOPC Builder flow.
  • Added support for EDA page and an option that creates a netlist for use by third-party synthesis tools.
  • Reorganized the user guide to make finding information easier and more efficient.
Level Two Title