Intel® Stratix® 10 DX FPGA Development Kit User Guide

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ID 683561
Date 9/25/2023
Public
Document Table of Contents
Document Table of Contents x
1. Getting Started 2. Development Kit Overview 3. Power Up the Development Kit 4. Board Test System (BTS) 5. Development Kit Hardware and Configuration 6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide A. Development Kit Components B. Safety and Regulatory Information C. Compliance and Conformity Information
1. Getting Started x
1.1. About this Document 1.2. Installing the Intel® Quartus® Prime Pro Edition Software 1.3. Downloading the Board Package 1.4. Installing the Driver for Intel FPGA Download Cable II
1.2. Installing the Intel® Quartus® Prime Pro Edition Software x
1.2.1. Activating Your License
2. Development Kit Overview x
2.1. Supported Features 2.2. Recommended Operating Conditions 2.3. Handling the Board
3. Power Up the Development Kit x
3.1. Default Switch Settings 3.2. Connectors and LEDs 3.3. Performing Board Restore through Board Test System (BTS) 3.4. Controlling On-board Clock
4. Board Test System (BTS) x
4.1. Preparing the Development Kit 4.2. Running the Board Test System 4.3. Using the Board Test System 4.4. Smart VID Setting
4.3. Using the Board Test System x
4.3.1. Configure Menu 4.3.2. Sys Info Tab 4.3.3. GPIO Tab 4.3.4. QSFP Tab 4.3.5. Component DDR4 CH0 Tab 4.3.6. Component DDR4 CH1 Tab 4.3.7. DDR4 DIMM CH0 Tab 4.3.8. DDR4 DIMM CH1 Tab 4.3.9. Power Monitor 4.3.10. Clock Controller
5. Development Kit Hardware and Configuration x
5.1. FPGA Configuration 5.2. Programming the FPGA Over Intel® FPGA Download Cable 5.3. Configuration Modes
5.3. Configuration Modes x
5.3.1. Avalon® Streaming Interface x8 Mode 5.3.2. JTAG Mode
5.3.1. Avalon® Streaming Interface x8 Mode x
Avalon® Streaming Interface x8 Configuration Guideline
A. Development Kit Components x
A.1. Components Overview A.2. Power, Thermal, and Mechanical Considerations A.3. Clock Circuits A.4. Memory Interface A.5. PCIe Interface A.6. UPI Interface A.7. Transceiver Signals: PCIe and UPI Interface A.8. SlimSAS Connector A.9. QSFP Network Interface A.10. I2C Interface A.11. QSPI Flash Memory
A.2. Power, Thermal, and Mechanical Considerations x
A.2.1. Power Guidelines A.2.2. Thermal Requirements A.2.3. Mechanical Requirements
A.2.1. Power Guidelines x
A.2.1.1. Power Distribution A.2.1.2. Power Sequence A.2.1.3. Power Measurement
A.2.2. Thermal Requirements x
A.2.2.1. Operating Conditions A.2.2.2. Temperature Monitoring
A.9. QSFP Network Interface x
A.9.1. Dual Port Controller
A.11. QSPI Flash Memory x
A.11.1. Configuration QSPI Flash Memory A.11.2. NIOS QSPI Flash Memory
B. Safety and Regulatory Information x
B.1. Safety Warnings B.2. Safety Cautions
1. Getting Started
2. Development Kit Overview
3. Power Up the Development Kit
4. Board Test System (BTS)
5. Development Kit Hardware and Configuration
6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide
A. Development Kit Components
B. Safety and Regulatory Information
C. Compliance and Conformity Information

2.1. Supported Features

Table 3.  Supported Features
Category Features
Intel® Stratix® 10 DX FPGA
  • 0.85-0.89V/VID-adjustable VCC core, 2912 pin BGA package
  • P-Tile transceivers supporting PCIe Gen4 or UPI
  • E-Tile transceivers supporting 28Gbps NRZ and 56Gbps PAM4
FPGA configuration
  • Partial reconfiguration support
  • CVP configuration support
  • 2Gb QSPI Flash
  • Storage for one configuration image in flash
  • JTAG header for device programming
  • Built-in Intel® FPGA Download Cable for device programming
Programmable clock sources
  • 312.53125 Mhz and 156.25 MHz Differential LVDS for QSFP
  • 100 Mhz Differential LVDS for PCIe
  • 133 Mhz Differential LVDS for Memory
  • 125 Mhz Configuration clock
  • 100 Mhz Differential LVDS for IO banks
Transceiver interfaces
  • PCIe x16 interface supporting Gen4 End-Point mode connected to a x16 PCIe edge connector (gold edge fingers)
  • 2x standard QSFP56 optical module interfaces connected to the E-tile transceivers
  • 3x UPI or PCIe interface supporting UPI x20 at 11.2Gbps or PCIe x16 at 16Gbps via SlimSAS connectors (cables shipped separately)
Memory interfaces
  • Two on-board independent single rank DDR4 x72 (ECC) channels operating at 1200 MHz (DDR4-2400)
  • Two DIMM sockets supporting DDR4 DIMM or Intel’s Optane® DC Persistent memory module
Communication ports
  • 2xQSFP28 optical interface port
  • JTAG header
  • USB (Micro USB) on-board Intel® FPGA Download Cable II
  • System I2C header
Buttons, Switches, and LEDs
  • System Reset Push button
  • CPU Reset Push button
  • PCIe Reset Push button
  • Four dedicated User LEDs
  • Link LED of each QSFP28 port to indicate the link and data transceiver
  • Two dedicated configuration status LEDs
Heatsink and Fan
  • Air-cooled heatsink assembly
  • Red Over-Temperature Warning LED Indicator
Power
  • PCIe input power including required 2x4 AUX power connector
  • Blue Power-On LED
  • On/Off Slide Power Switch for benchtop operation
  • On board power and temperature measurement circuitry
Mechanical
  • PCIe standard height form factor
  • 4.376” x 10.0” board size
  • 2 Slots height with heatsink
Level Two Title