Intel® Stratix® 10 DX FPGA Development Kit User Guide

Download PDF
ID 683561
Date 9/25/2023
Public
Document Table of Contents
Document Table of Contents x
1. Getting Started 2. Development Kit Overview 3. Power Up the Development Kit 4. Board Test System (BTS) 5. Development Kit Hardware and Configuration 6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide A. Development Kit Components B. Safety and Regulatory Information C. Compliance and Conformity Information
1. Getting Started x
1.1. About this Document 1.2. Installing the Intel® Quartus® Prime Pro Edition Software 1.3. Downloading the Board Package 1.4. Installing the Driver for Intel FPGA Download Cable II
1.2. Installing the Intel® Quartus® Prime Pro Edition Software x
1.2.1. Activating Your License
2. Development Kit Overview x
2.1. Supported Features 2.2. Recommended Operating Conditions 2.3. Handling the Board
3. Power Up the Development Kit x
3.1. Default Switch Settings 3.2. Connectors and LEDs 3.3. Performing Board Restore through Board Test System (BTS) 3.4. Controlling On-board Clock
4. Board Test System (BTS) x
4.1. Preparing the Development Kit 4.2. Running the Board Test System 4.3. Using the Board Test System 4.4. Smart VID Setting
4.3. Using the Board Test System x
4.3.1. Configure Menu 4.3.2. Sys Info Tab 4.3.3. GPIO Tab 4.3.4. QSFP Tab 4.3.5. Component DDR4 CH0 Tab 4.3.6. Component DDR4 CH1 Tab 4.3.7. DDR4 DIMM CH0 Tab 4.3.8. DDR4 DIMM CH1 Tab 4.3.9. Power Monitor 4.3.10. Clock Controller
5. Development Kit Hardware and Configuration x
5.1. FPGA Configuration 5.2. Programming the FPGA Over Intel® FPGA Download Cable 5.3. Configuration Modes
5.3. Configuration Modes x
5.3.1. Avalon® Streaming Interface x8 Mode 5.3.2. JTAG Mode
5.3.1. Avalon® Streaming Interface x8 Mode x
Avalon® Streaming Interface x8 Configuration Guideline
A. Development Kit Components x
A.1. Components Overview A.2. Power, Thermal, and Mechanical Considerations A.3. Clock Circuits A.4. Memory Interface A.5. PCIe Interface A.6. UPI Interface A.7. Transceiver Signals: PCIe and UPI Interface A.8. SlimSAS Connector A.9. QSFP Network Interface A.10. I2C Interface A.11. QSPI Flash Memory
A.2. Power, Thermal, and Mechanical Considerations x
A.2.1. Power Guidelines A.2.2. Thermal Requirements A.2.3. Mechanical Requirements
A.2.1. Power Guidelines x
A.2.1.1. Power Distribution A.2.1.2. Power Sequence A.2.1.3. Power Measurement
A.2.2. Thermal Requirements x
A.2.2.1. Operating Conditions A.2.2.2. Temperature Monitoring
A.9. QSFP Network Interface x
A.9.1. Dual Port Controller
A.11. QSPI Flash Memory x
A.11.1. Configuration QSPI Flash Memory A.11.2. NIOS QSPI Flash Memory
B. Safety and Regulatory Information x
B.1. Safety Warnings B.2. Safety Cautions
1. Getting Started
2. Development Kit Overview
3. Power Up the Development Kit
4. Board Test System (BTS)
5. Development Kit Hardware and Configuration
6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide
A. Development Kit Components
B. Safety and Regulatory Information
C. Compliance and Conformity Information

A.3. Clock Circuits

All clocks are supplied by two on-board low-jitter programmable clock generator circuits. The following figure depicts the clock connection to the Intel® Stratix® 10 DX FPGA:
Figure 40. Clock Connection
Table 11.  On-board Oscillators
Signal Name Frequency (MHz) I/O Standard Application
Source: U7 (Si5332A)
CLK_100M_FPGA_3H_P 100 LVDS FPGA Fabric Clock

Bank 3H
CLK_100M_FPGA_3H_N LVDS
CLK_125M_LVC1_CONFIG 125 LVCMOS FPGA Config Clock
CLK_133M_DDR4_0_P 133.33 LVDS FPGA Fabric Clock

Bank 3J
CLK_133M_DDR4_0_N LVDS
CLK_133M_DDR4_1_P 133.33 LVDS FPGA Fabric Clock

Bank 2L
CLK_133M_DDR4_1_N LVDS
CLK_133M_DIMM_1_P 133.33 LVDS FPGA Fabric Clock

Bank 3B
CLK_133M_DIMM_1_N LVDS
CLK_133M_DIMM_0_P 133.33 LVDS FPGA Fabric Clock

Bank 2C
CLK_133M_DIMM_0_N LVDS
CLK_100M_FPGA_3L_0_P 100 LVDS FPGA Fabric Clock

Bank 3L
CLK_100M_FPGA_3L_0_N LVDS
CLK_100M_TEST_P 100 HCSL Clock for bench test
CLK_100M_TEST_N HCSL
Source: U9 (Si5391A)
CLk_156M.25M_QSFP1_P 156.25 LVPECL Reference Clock for Transceivers 9A
CLk_156M.25M_QSFP1_N LVPECL
CLk_156M.25M_QSFP0_P 156.25 LVPECL Reference Clock for Transceivers 9A
CLk_156.25M_QSFP0_N LVPECL
CLk_312M.50M_QSFP0_P 312.50 LVPECL Reference Clock for Transceivers 9A
CLk_312M.50M_QSFP0_N LVPECL
CLk_312M.50M_QSFP1_P 312.50 LVPECL Reference Clock for Transceivers 9A
CLk_312M.50M_QSFP1_N LVPECL
CLk_312M.50M_QSFP2_P 312.50 LVPECL Reference Clock for Transceivers 9A
CLk_312M.50M_QSFP2_N LVPECL
CLK_100M_FPGA_2I_P 100 LVDS FPGA Fabric Clock

Bank 2I
CLK_100M_FPGA_2I_N LVDS
CLK_100M_FPGA_2J_1_P 100 LVDS FPGA Fabric Clock

Bank 2J
CLK_100M_FPGA_2J_1_N LVDS
CLK_100M_FPGA_2J_0_P 100 LVDS FPGA Fabric Clock

Bank 2J
CLK_100M_FPGA_2J_0_N LVDS
CLK_100M_Si5391_P 100 LVDS Clock to U7

Input 2
CLK_100M_Si5391_N LVDS
The default clock frequencies are as listed in the table. All the clock frequencies can be changed by using the Clock GUI.
Level Two Title