Intel® Stratix® 10 DX FPGA Development Kit User Guide

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ID 683561
Date 9/25/2023
Public
Document Table of Contents
Document Table of Contents x
1. Getting Started 2. Development Kit Overview 3. Power Up the Development Kit 4. Board Test System (BTS) 5. Development Kit Hardware and Configuration 6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide A. Development Kit Components B. Safety and Regulatory Information C. Compliance and Conformity Information
1. Getting Started x
1.1. About this Document 1.2. Installing the Intel® Quartus® Prime Pro Edition Software 1.3. Downloading the Board Package 1.4. Installing the Driver for Intel FPGA Download Cable II
1.2. Installing the Intel® Quartus® Prime Pro Edition Software x
1.2.1. Activating Your License
2. Development Kit Overview x
2.1. Supported Features 2.2. Recommended Operating Conditions 2.3. Handling the Board
3. Power Up the Development Kit x
3.1. Default Switch Settings 3.2. Connectors and LEDs 3.3. Performing Board Restore through Board Test System (BTS) 3.4. Controlling On-board Clock
4. Board Test System (BTS) x
4.1. Preparing the Development Kit 4.2. Running the Board Test System 4.3. Using the Board Test System 4.4. Smart VID Setting
4.3. Using the Board Test System x
4.3.1. Configure Menu 4.3.2. Sys Info Tab 4.3.3. GPIO Tab 4.3.4. QSFP Tab 4.3.5. Component DDR4 CH0 Tab 4.3.6. Component DDR4 CH1 Tab 4.3.7. DDR4 DIMM CH0 Tab 4.3.8. DDR4 DIMM CH1 Tab 4.3.9. Power Monitor 4.3.10. Clock Controller
5. Development Kit Hardware and Configuration x
5.1. FPGA Configuration 5.2. Programming the FPGA Over Intel® FPGA Download Cable 5.3. Configuration Modes
5.3. Configuration Modes x
5.3.1. Avalon® Streaming Interface x8 Mode 5.3.2. JTAG Mode
5.3.1. Avalon® Streaming Interface x8 Mode x
Avalon® Streaming Interface x8 Configuration Guideline
A. Development Kit Components x
A.1. Components Overview A.2. Power, Thermal, and Mechanical Considerations A.3. Clock Circuits A.4. Memory Interface A.5. PCIe Interface A.6. UPI Interface A.7. Transceiver Signals: PCIe and UPI Interface A.8. SlimSAS Connector A.9. QSFP Network Interface A.10. I2C Interface A.11. QSPI Flash Memory
A.2. Power, Thermal, and Mechanical Considerations x
A.2.1. Power Guidelines A.2.2. Thermal Requirements A.2.3. Mechanical Requirements
A.2.1. Power Guidelines x
A.2.1.1. Power Distribution A.2.1.2. Power Sequence A.2.1.3. Power Measurement
A.2.2. Thermal Requirements x
A.2.2.1. Operating Conditions A.2.2.2. Temperature Monitoring
A.9. QSFP Network Interface x
A.9.1. Dual Port Controller
A.11. QSPI Flash Memory x
A.11.1. Configuration QSPI Flash Memory A.11.2. NIOS QSPI Flash Memory
B. Safety and Regulatory Information x
B.1. Safety Warnings B.2. Safety Cautions
1. Getting Started
2. Development Kit Overview
3. Power Up the Development Kit
4. Board Test System (BTS)
5. Development Kit Hardware and Configuration
6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide
A. Development Kit Components
B. Safety and Regulatory Information
C. Compliance and Conformity Information

A.2.1.1. Power Distribution

The power distribution system on the Intel® Stratix® 10 DX FPGA Development Kit is shown below.
Figure 34. Power Tree Diagram
Table 9.  Power Supply List
Source Name Power Name Maximum Output Current (A) Description
ED8401(U47) VCC 160 Core logic power
VCCP Periphery power
EN2260 (U230) 0.9V S10_VCCERAM 53 Embedded memory and digital transceiver power
VCCPLLDIG_SDM Digital PLL power for SDM
S10_VCCFUSE_GXP Fuse power for P-Tile
S10_VCCRT_GXP Analog power for high speed circuits P-Tile
S10_VCCRT_GXE Analog power for high speed circuits E-Tile
S10_VCCRTPLL_GXE PLL power for E-Tile
EN2130H (U113) 1.8V S10_VCCPLL_SDM 18 SDM PLL power
S10_VCCADC ADC power
S10_VCCA_PLL Analog power for PLL
S10_VCCPT  
S10_VCCBAT  
EN63A0 (U186) 1.8V S10_VCCH_GXP 12 Analog power for P-Tile
S10_VCCCLK_GXP Clock power for P-Tile
EN63A0 (U184) 1.1V S10_VCCH_GXE 8 Analog power for E-Tile
EP53F8QI (U78) 2.5V S10_VCCCLK_GXE 1.5

Clock power for E-Tile

2.5V 2.5V for others on board
EP53F8QI (U76) 2.4V S10_VCCFUSEWR_SDM 0.5 Fuse power for SDM
EN6382QII (U188) 1.8V S10_VCCIO 6 Power for IO banks of Intel® Stratix® 10
EZ6303QI (U116) 1.2V M10_VCC_1.2V 1 Core power for Intel® MAX® 10
M10_VCCDPLL PLL power for Intel® MAX® 10
EZ6303QI (U116) 2.5V M10_VCCA/VCC_ADC 0.2 Power for Intel® MAX® 10 ADC circuits
FP53F8QI (U79) 1.8V M10_VCCIO 1 Power for 1.8V IOs of Intel® MAX® 10
EM2130H(U101) 3.3V 3.3V_REG_INST 30 System 3.3V rail
EV1320QI (U164) 0.6V 0p6V_DDR4_VTT_CH00 0.02 Termination power for on-board DDR4
EP53F8QI (U163) 2.5V 2V5_DDR4_CH00 0.1 2.5V rail for DDR4
EN63A0 (U159) 1.2V S10_1v2OUT_CH00 12 Memory IO power for Ch00
EV1320QI (U166) 0.6V 0p6V_DDR4_VTT_CH11 0.02 Termination power for on-board DDR4
EP53F8QI (U165) 2.5V 2V5_DDR4_CH11 0.1 2.5V rail for DDR4
EN63A0 (U157) 1.2V S10_1v2OUT_CH11 12 Memory IO power for Ch00
MAX16550 (U217) 12V 12V_AUX2_IN 20 12V rail from AUX Power connector
MAX16550 (U96) 12V 12V_PCIe_SLOT 5.5 12V rail from PCIe Edge Connector
Level Two Title