Intel® Stratix® 10 DX FPGA Development Kit User Guide

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ID 683561
Date 9/25/2023
Public
Document Table of Contents
Document Table of Contents x
1. Getting Started 2. Development Kit Overview 3. Power Up the Development Kit 4. Board Test System (BTS) 5. Development Kit Hardware and Configuration 6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide A. Development Kit Components B. Safety and Regulatory Information C. Compliance and Conformity Information
1. Getting Started x
1.1. About this Document 1.2. Installing the Intel® Quartus® Prime Pro Edition Software 1.3. Downloading the Board Package 1.4. Installing the Driver for Intel FPGA Download Cable II
1.2. Installing the Intel® Quartus® Prime Pro Edition Software x
1.2.1. Activating Your License
2. Development Kit Overview x
2.1. Supported Features 2.2. Recommended Operating Conditions 2.3. Handling the Board
3. Power Up the Development Kit x
3.1. Default Switch Settings 3.2. Connectors and LEDs 3.3. Performing Board Restore through Board Test System (BTS) 3.4. Controlling On-board Clock
4. Board Test System (BTS) x
4.1. Preparing the Development Kit 4.2. Running the Board Test System 4.3. Using the Board Test System 4.4. Smart VID Setting
4.3. Using the Board Test System x
4.3.1. Configure Menu 4.3.2. Sys Info Tab 4.3.3. GPIO Tab 4.3.4. QSFP Tab 4.3.5. Component DDR4 CH0 Tab 4.3.6. Component DDR4 CH1 Tab 4.3.7. DDR4 DIMM CH0 Tab 4.3.8. DDR4 DIMM CH1 Tab 4.3.9. Power Monitor 4.3.10. Clock Controller
5. Development Kit Hardware and Configuration x
5.1. FPGA Configuration 5.2. Programming the FPGA Over Intel® FPGA Download Cable 5.3. Configuration Modes
5.3. Configuration Modes x
5.3.1. Avalon® Streaming Interface x8 Mode 5.3.2. JTAG Mode
5.3.1. Avalon® Streaming Interface x8 Mode x
Avalon® Streaming Interface x8 Configuration Guideline
A. Development Kit Components x
A.1. Components Overview A.2. Power, Thermal, and Mechanical Considerations A.3. Clock Circuits A.4. Memory Interface A.5. PCIe Interface A.6. UPI Interface A.7. Transceiver Signals: PCIe and UPI Interface A.8. SlimSAS Connector A.9. QSFP Network Interface A.10. I2C Interface A.11. QSPI Flash Memory
A.2. Power, Thermal, and Mechanical Considerations x
A.2.1. Power Guidelines A.2.2. Thermal Requirements A.2.3. Mechanical Requirements
A.2.1. Power Guidelines x
A.2.1.1. Power Distribution A.2.1.2. Power Sequence A.2.1.3. Power Measurement
A.2.2. Thermal Requirements x
A.2.2.1. Operating Conditions A.2.2.2. Temperature Monitoring
A.9. QSFP Network Interface x
A.9.1. Dual Port Controller
A.11. QSPI Flash Memory x
A.11.1. Configuration QSPI Flash Memory A.11.2. NIOS QSPI Flash Memory
B. Safety and Regulatory Information x
B.1. Safety Warnings B.2. Safety Cautions
1. Getting Started
2. Development Kit Overview
3. Power Up the Development Kit
4. Board Test System (BTS)
5. Development Kit Hardware and Configuration
6. Document Revision History for Intel® Stratix® 10 DX FPGA Development Kit User Guide
A. Development Kit Components
B. Safety and Regulatory Information
C. Compliance and Conformity Information

A.2.1.2. Power Sequence

The Intel® Stratix® 10 DX FPGA device requires proper power up and power down sequences.
Table 10.  Power Sequencing Groups
Group 1 Group 2 Group 3
VCCL/VCC (0.89)

VCCERAM (0.9)

VCCPLLDIG_SDM (0.9)

VCCRT_GXP (0.9)

VCCRT_GXE (0.9)

VCCRTPLL_GXE (0.9)

VCCFUSE_GXP (0.9)

VCCH_GXE (1.1)

VCCH_GXP (1.8)

VCCADC (1.8)

VCCPLL_SDM (1.8)

VCCAPLL (1.8)

VCCIO (2.5)

VCCIO (1.8)

VCCIO (1.2, 1.25, 1.35, 1.5, 1.8)

VCCFUSEWR_SDM (2.4)

VCCN_SDM (1.8)

VCCIO3 (1.5, 1.8, 2.5, 3.0)

  • Required power up sequence: Group 1 > Group 2 > Group 3
  • Required power down sequence: Group 3 > Group 2 > Group 1
  • I/O pins are tri-stated during power-up or down sequence when the proper power sequence is followed. I/O pins should not be driven externally during this time or excess I/O pin current can result.
  • Power supplies in each group can be ramped up in any order.
  • The total power supply ramp-down time must not exceed 100 ms.
  • Ramp-up the last power supply of Group 1 to 90% (0.72) before ramping up the Group 2 supplies. Ramp up the last power supply of Group 2 to 90% (1.62V) before ramping up the Group 3 supplies.
  • VCCBAT_SDM can be powered up anytime.
  • To use CvP/autonomous hard IP, the total time must be within 10 ms, from the first power supply ramp-up to the last power supply ramp-up.
    Note: The POR delay time in Intel® Stratix® 10 DX FPGA is always within 2ms.
  • VCCL and VCC should be tied together at customer board.
  • VCCPLL_HPS and VCCPLL_SDM should be tied together at customer board.
  • VCCPLLDIG_SDM and VCCERAM should be tied together at customer board with a filter.
  • VCCADC and VCCA should be tied together at customer board with or without a filter.
  • VCCERT, VCCERT_PLL and VCCERAM should be tied together at customer board with or without a filter and should ramp up together for better current control.
    • Noise mask specifications must be met.
    • Use of an LC Filter is proposed to enable sourcing VCCERT, VCCERT_PLL from VCCERAM.
  • VCCN_SDM has to stay in Group 3. It cannot be moved to Group 2 or merged with any Group 2 regulator.
  • VCCFUSE_GXP is always connected to VCCERAM on customer board. For only internal testing purposes, VCCFUSE_GXP is connected to VCCR.
  • All power rails must ramp up monotonically.
  • All power rails must ramp up to full rail in Tramp specified in the Intel® Stratix® 10 Device Datasheet.
  • Ensure (VCCIO - VCCPT) is less than 1.92 to avoid damage to the device
  • Hot socket is not supported in Intel® Stratix® 10 DX FPGA.
Figure 35. Power Sequence Flow Diagram
Level Two Title