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1.1. Release Information
1.2. Device Family Support
1.3. Parameters
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface
1.6. Commands and Responses
1.7. Specifying the Command and Response FIFO Depths
1.8. Enabling Cryptographic Services
1.9. Using the Mailbox Client Intel® FPGA IP
1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
1.11. Nios® II and Nios® V Processors HAL Driver
1.12. Mailbox Client Intel FPGA IP User Guide Archives
1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
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1.11.2.2. Error Codes
In case of success, the LibRSU HAL APIs return the value 0; otherwise, the LibRSU HAL APIs return the negative values shown below.
#define ELIB 1 /* Error Library */ #define ECFG 2 /* Error Configuration */ #define ESLOTNUM 3 /* Error Slot Number */ #define EFORMAT 4 /* Error Format */ #define EERASE 5 /* Error Erase */ #define EPROGRAM 6 /* Error Program */ #define ECMP 7 /* Error Compare */ #define ESIZE 8 /* Error Size */ #define ENAME 9 /* Error Name */ #define EFILEIO 10 /* Error File IO */ #define ECALLBACK 11 /* Error Callback */ #define ELOWLEVEL 12 /* Error Low Level */ #define EWRPROT 13 /* Error Write Protection */ #define EARGS 14 /* Error Argument */ #define ECORRUPTED_CPB 15 /* Error Corrupted CPB */ #define ECORRUPTED_SPT 16 /* Error Corrupted SPT */