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1.1. Release Information
1.2. Device Family Support
1.3. Parameters
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface
1.6. Commands and Responses
1.7. Specifying the Command and Response FIFO Depths
1.8. Enabling Cryptographic Services
1.9. Using the Mailbox Client Intel® FPGA IP
1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
1.11. Nios® II and Nios® V Processors HAL Driver
1.12. Mailbox Client Intel FPGA IP User Guide Archives
1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
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1.11.2.1. Configuration Parameter
The LibRSU HAL API configuration parameters are stored in Board Support Package (BSP) setting file. You can edit the configuration parameters through the BSP Driver tab. If they are not specified, the LibRSU HAL API uses the default value.
Variable | Default Value | Description |
---|---|---|
rsu_protected_slot | -1 | Allows protection on a certain slot number. Only slots between 0 and 31 can be protected by this feature. By default (rsu_protected_slot = -1), no slot is protected. |
rsu_log_level | 3 | Allows customization on how much logging information is displayed. The valid inputs are 1,2 and 3. By default, the log level is set as 3 and all logging information is displayed. |
enable_spt_checksum | Disable | Enables check and maintenance of the SPT checksum. By default, the SPT checksum feature is disabled. |
enable_rsu | Disable | Enables the RSU functions. By default, it is disabled and the Mailbox Client Intel FPGA IP core performs without the RSU functions. |
fpga_device
|
Disable | Allows configuration targeting the selected Intel FPGA devices. By default, the configuration targets Agilex™ 7 devices, thus the Stratix® 10 setting is disabled. |