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1.1. Release Information
1.2. Device Family Support
1.3. Parameters
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface
1.6. Commands and Responses
1.7. Specifying the Command and Response FIFO Depths
1.8. Enabling Cryptographic Services
1.9. Using the Mailbox Client Intel® FPGA IP
1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
1.11. Nios® II and Nios® V Processors HAL Driver
1.12. Mailbox Client Intel FPGA IP User Guide Archives
1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
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1.4.1. Clock and Reset Interfaces
Signal Role | Width | Direction | Description |
---|---|---|---|
clk | 1 | Input | Input clock to clock the Mailbox Client Intel® FPGA IP. The maximum frequency is 250 MHz. |
reset | 1 | Input | Reset that resets the Mailbox Client Intel® FPGA IP. To reset the IP, assert the reset signal high for at least 2 clk cycles.
To ensure the Mailbox Client Intel® FPGA IP functions correctly when the device enters user mode, your design must include the Reset Release Intel® FPGA IP to hold the reset until the FPGA fabric entered user mode. Intel recommends using a reset synchronizer when connecting the user reset or output of the Reset Release Intel® FPGA IP to the reset port of the Mailbox Client Intel® FPGA IP. To implement the reset synchronizer, use the Reset Bridge Intel® FPGA IP available in the Platform Designer.
Note: For IP instantiation and connection guidelines in the Platform Designer, refer to the Required Communication and Host Components for the Remote System Update Design Example figure in the Stratix® 10 Configuration User Guide.
Note: For IP instantiation guidelines, refer to the respective device's Configuration User Guide.
|
irq | 1 | Output | Interrupt signal. Drives the value of the AND of the interrupt status and interrupt enable registers. |