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1.1. Release Information
1.2. Device Family Support
1.3. Parameters
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface
1.6. Commands and Responses
1.7. Specifying the Command and Response FIFO Depths
1.8. Enabling Cryptographic Services
1.9. Using the Mailbox Client Intel® FPGA IP
1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
1.11. Nios® II and Nios® V Processors HAL Driver
1.12. Mailbox Client Intel FPGA IP User Guide Archives
1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
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1.4.2. Avalon® Memory-Mapped Interface
The Avalon® memory-mapped interface is standard memory-mapped interface. For detailed definitions of these signals, refer to the Avalon® Memory-Mapped Interface chapter in the Avalon® Interface Specifications.
Signal Role | Width | Direction | Description |
---|---|---|---|
avmm_address | 4 | Input | Avalon® memory-mapped interface address. |
avmm_write | 1 | Input | Avalon® memory-mapped interface write request. |
avmm_read | 1 | Input | Avalon® memory-mapped interface read request. |
avmm_writedata | 32 | Input | Avalon® memory-mapped interface write data bus. |
avmm_readdata | 32 | Output | Avalon® memory-mapped interface read data bus. |
avmm_readdatavalid | 1 | Output | Avalon® memory-mapped interface read data valid. |
avmm_waitrequest | 1 | Output | Avalon® memory-mapped interface wait request. |