Agilex™ 7 FPGA I-Series Development Kit User Guide

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ID 683288
Date 12/20/2024
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Visible to Intel only — GUID: yme1629310525310

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Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Board 3.2. Default Settings 3.3. Performing Board Restore through Quartus® Prime Programmer 3.4. Generating a POF Image to Program the Flash 3.5. Programming the Generated POF Image 3.6. The Required SmartVID QSF Assignments to Compile a Design
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-board Power through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The RAM Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab
A. Development Kit Components x
A.1. Board Overview A.2. Agilex™ 7 FPGA I-Series A.3. PCIe* and CXL Interfaces A.4. MCIO Connector A.5. MCIO Cable Assembly Information A.6. Network Interfaces A.7. Port Controller A.8. FPGA Configuration A.9. Supported Configuration Modes A.10. Memory Interfaces A.11. I2C A.12. Clock Circuits A.13. System Power A.14. Temperature Monitoring A.15. Mechanical Requirements A.16. Board Thermal Requirements A.17. Board Operating Conditions A.18. Over Temperature Warning LED
A.13. System Power x
A.13.1. Power Guidelines A.13.2. Power Distribution System A.13.3. Power Sequence A.13.4. Power Measurement
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.9. Supported Configuration Modes

  • The development board supports two configuration modes: Avalon® streaming interface x8 and JTAG.
  • The default configuration is Avalon® streaming interface x8 using a 2 Gb QSPI flash device.
  • JTAG configuration is supported by using either the embedded Intel® FPGA Download Cable II or the Intel® FPGA Download Cable II dongle.

Avalon® Streaming Interface x8 Mode

The SDM block in the Agilex™ 7 device controls the configuration process and interface. The MAX® 10 System Controller (U34) interfaces to the Agilex™ 7 FPGA in the Avalon® streaming interface x8 mode. The MAX® 10 also interfaces to the QSPI flash in the active serial (AS) x4 mode. For the AS x4 mode, MSEL[2:0] configuration pin strapping (SW2) must be set to [110]. The flash device is Micron Technology* 1.8 V core, 1.8 V I/O 2 Gigabit CFI NOR-type device (P/N: MT25QL02GBB8E12-0).

JTAG Configuration Mode

The JTAG switch implemented in the MAX® 10 System Controller (U34) allows the selection of devices to be included in the JTAG chain. It is done by the settings of the DIP switch SW8. The embedded Intel® FPGA Download Cable II (or external download cable) or PCIe* JTAG can be selected as the source for programming the devices on the chain. The embedded Intel® FPGA Download Cable II is the default setting for this configuration mode.

Figure 44. JTAG Block Diagram

The on-board Intel® FPGA Download Cable II is implemented in a MAX® 10 device. A micro-USB connector connects to a CY7C68013A USB2 PHY provides the data to MAX® 10. This allows configuration of the FPGA using a USB cable directly connected to a PC running the Quartus® Prime software without requiring the external download cable dongle. An external download cable dongle can also be used on J10 to configure the FPGA.

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