Agilex™ 7 FPGA I-Series Development Kit User Guide

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ID 683288
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide A. Development Kits Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Box Contents 1.3. Operating Conditions
2. Getting Started x
2.1. About Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. About Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch Settings 3.3. How to Generate a POF Image to Program the Flash 3.4. How to Program the Generated POF Image 3.5. The Required SmartVID QSF Assignments to Compile a Design
3.2. Default Switch Settings x
3.2.1. Default Settings 3.2.2. Perform Board Restore through Quartus® Prime Programmer
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-board Clock through Clock Controller GUI 4.4. Monitor On-board Power through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The RAM Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab
A. Development Kits Components x
A.1. Board Overview A.2. Agilex™ 7 FPGA I-Series A.3. PCIe* and CXL Interfaces A.4. MCIO Connector A.5. MCIO Cable Assembly Information A.6. Network Interfaces A.7. Port Controller A.8. FPGA Configuration A.9. Supported Configuration Modes A.10. Memory Interfaces A.11. I2C A.12. Clock Circuits A.13. System Power A.14. Temperature Monitoring A.15. Mechanical Requirements A.16. Board Thermal Requirements A.17. Board Operating Conditions A.18. Over Temperature Warning LED
A.13. System Power x
A.13.1. Power Guidelines A.13.2. Power Distribution System A.13.3. Power Sequence A.13.4. Power Measurement
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide
A. Development Kits Components
B. Additional Information

A.9. Supported Configuration Modes

  • The development board supports two configuration modes: Avalon® -ST (AVST) x8 and JTAG.
  • The default configuration is AVST x8 using a 2 Gb QSPI flash device.
  • JTAG configuration is supported by using either the embedded Intel® FPGA Download Cable II or the Intel® FPGA Download Cable II dongle.

Avalon® -ST (AVST) x8 Mode

The SDM block in the Agilex™ 7 device controls the configuration process and interface. The MAX® 10 System Controller (U34) interfaces to the Agilex™ 7 FPGA in the AVST x8 mode. The MAX® 10 also interfaces to the QSPI flash in the active serial (AS) x4 mode. For the AS x4 mode, MSEL[2:0] configuration pin strapping (SW2) must be set to [110]. The flash device is Micron Technology 1.8 V core, 1.8V I/O 2 Gigabit CFI NOR-type device (P/N: MT25QL02GBB8E12-0).

JTAG Configuration Mode

The JTAG switch implemented in the MAX® 10 System Controller (U34) allows the selection of devices to be included in the JTAG chain. It is done by the settings of the DIP switch SW8. The embedded Intel® FPGA Download Cable II (or external download cable) or PCIe* JTAG can be selected as the source for programming the devices on the chain. The embedded Intel® FPGA Download Cable II is the default setting for this configuration mode.

Figure 40. JTAG Block Diagram

The on-board Intel® FPGA Download Cable II is implemented in a MAX® 10 device. A micro-USB connector connects to a CY7C68013A USB2 PHY provides the data to MAX® 10. This allows configuration of the FPGA using a USB cable directly connected to a PC running the Quartus® Prime software without requiring the external download cable dongle. An external download cable dongle can also be used on J10 to configure the FPGA.

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