Agilex™ 7 FPGA I-Series Development Kit User Guide

ID 683288
Date 5/31/2024
Public
Document Table of Contents

A.9. Supported Configuration Modes

  • The development board supports two configuration modes: Avalon® -ST (AVST) x8 and JTAG.
  • The default configuration is AVST x8 using a 2 Gb QSPI flash device.
  • JTAG configuration is supported by using either the embedded Intel® FPGA Download Cable II or the Intel® FPGA Download Cable II dongle.

Avalon® -ST (AVST) x8 Mode

The SDM block in the Agilex™ 7 device controls the configuration process and interface. The MAX® 10 System Controller (U34) interfaces to the Agilex™ 7 FPGA in the AVST x8 mode. The MAX® 10 also interfaces to the QSPI flash in the active serial (AS) x4 mode. For the AS x4 mode, MSEL[2:0] configuration pin strapping (SW2) must be set to [110]. The flash device is Micron Technology 1.8 V core, 1.8V I/O 2 Gigabit CFI NOR-type device (P/N: MT25QL02GBB8E12-0).

JTAG Configuration Mode

The JTAG switch implemented in the MAX® 10 System Controller (U34) allows the selection of devices to be included in the JTAG chain. It is done by the settings of the DIP switch SW8. The embedded Intel® FPGA Download Cable II (or external download cable) or PCIe* JTAG can be selected as the source for programming the devices on the chain. The embedded Intel® FPGA Download Cable II is the default setting for this configuration mode.

Figure 40. JTAG Block Diagram

The on-board Intel® FPGA Download Cable II is implemented in a MAX® 10 device. A micro-USB connector connects to a CY7C68013A USB2 PHY provides the data to MAX® 10. This allows configuration of the FPGA using a USB cable directly connected to a PC running the Quartus® Prime software without requiring the external download cable dongle. An external download cable dongle can also be used on J10 to configure the FPGA.