Agilex™ 7 FPGA I-Series Development Kit User Guide

ID 683288
Date 5/31/2024
Public
Document Table of Contents

A.6. Network Interfaces

The development kit supports two QSFPDD connectors each, connecting to the Agilex™ 7's F-tile (12A) transceivers. Each port can operate at 4x 58G or 8x 28G. These two ports support ZQSFP56 SR optical modules as well as the 3M DAC electrical cables. A Texas Instruments FPC202 dual-port controller serves as the low-speed signal aggregator that makes up the Dual 100Gpbs Ethernet interfaces. The FPC202 aggregates all low speed and I2C signals across two ports and presents it as a single management interface to the host.

The F-tile (12A) of the FPGA provides 16 general-purpose (FGT) transceiver channels, each 8-channel group is routed to one QSFPDD. The transceiver bank requires 156.25 MHz clocks for the 28 Gbps NRZ and 325.50 MHz clocks for the 56 Gbps PAM4. These clocks must have RPM jitter <250fs.

Figure 38. F-Tile Bank 12A Circuit