Agilex™ 7 FPGA I-Series Development Kit User Guide

ID 683288
Date 5/31/2024
Public
Document Table of Contents

A.3. PCIe* and CXL Interfaces

The Agilex™ 7 FPGA I-Series Development Kit supports two PCIe* /CXL Gen5 x16 interfaces using two out of the FPGA's three R-tiles, refer to Board Diagram.

  1. One R-tile (14C) supports PCIe* /CXL x16 connecting to the development kit's PCIe* edge connector. This interface supports x1, x4, x8, and x16 PCIe* Endpoint or CXL Endpoint.
  2. One R-tile (15C) connects to two 74-pin MCIO connectors that can be used as a CXL or PCIe* x16 interface in the Endpoint or Root Port mode. The MCIO connectors also carry SMBus/I2C, clock, and GPIO signals.
Note: To activate the CXL hard IP and receive CXL soft R-Tile Wrapper and Soft Support logic, purchase or activation of a separate CXL IP license is required for proper use with the Quartus® Prime Design Software. Contact your local Intel® sales representative for pricing details. To activate a free-of-charge 30- or 60-days trial IP license, please contact your local Intel® sales representative.