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Ixiasoft
A.1. Board Overview
A.2. Agilex™ 7 FPGA I-Series
A.3. PCIe* and CXL Interfaces
A.4. MCIO Connector
A.5. MCIO Cable Assembly Information
A.6. Network Interfaces
A.7. Port Controller
A.8. FPGA Configuration
A.9. Supported Configuration Modes
A.10. Memory Interfaces
A.11. I2C
A.12. Clock Circuits
A.13. System Power
A.14. Temperature Monitoring
A.15. Mechanical Requirements
A.16. Board Thermal Requirements
A.17. Board Operating Conditions
A.18. Over Temperature Warning LED
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Ixiasoft
A.4. MCIO Connector
The CXL or PCIe* interface is connected to two 74-pin MCIO connectors for 16 channels of transmit and receive signals of the R-tile (15C). Cables are used to connect this CXL or PCIe* link from the development kit to the host board or application-specific daughter cards.
Figure 36. MCIO Connector
Figure 37. MCIO Connector Circuit