Agilex™ 7 FPGA I-Series Development Kit User Guide

ID 683288
Date 5/31/2024
Public
Document Table of Contents

A.4. MCIO Connector

The CXL or PCIe* interface is connected to two 74-pin MCIO connectors for 16 channels of transmit and receive signals of the R-tile (15C). Cables are used to connect this CXL or PCIe* link from the development kit to the host board or application-specific daughter cards.
Figure 36. MCIO Connector
Figure 37. MCIO Connector Circuit