Agilex™ 7 FPGA I-Series Development Kit User Guide

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ID 683288
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide A. Development Kits Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Box Contents 1.3. Operating Conditions
2. Getting Started x
2.1. About Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. About Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch Settings 3.3. How to Generate a POF Image to Program the Flash 3.4. How to Program the Generated POF Image 3.5. The Required SmartVID QSF Assignments to Compile a Design
3.2. Default Switch Settings x
3.2.1. Default Settings 3.2.2. Perform Board Restore through Quartus® Prime Programmer
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-board Clock through Clock Controller GUI 4.4. Monitor On-board Power through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The RAM Tab Start Stop Performance Indicators Test Control Error Control
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab
A. Development Kits Components x
A.1. Board Overview A.2. Agilex™ 7 FPGA I-Series A.3. PCIe* and CXL Interfaces A.4. MCIO Connector A.5. MCIO Cable Assembly Information A.6. Network Interfaces A.7. Port Controller A.8. FPGA Configuration A.9. Supported Configuration Modes A.10. Memory Interfaces A.11. I2C A.12. Clock Circuits A.13. System Power A.14. Temperature Monitoring A.15. Mechanical Requirements A.16. Board Thermal Requirements A.17. Board Operating Conditions A.18. Over Temperature Warning LED
A.13. System Power x
A.13.1. Power Guidelines A.13.2. Power Distribution System A.13.3. Power Sequence A.13.4. Power Measurement
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide
A. Development Kits Components
B. Additional Information

4.2.6. The RAM Tab

This tab allows you to read and write DDR4-COMP0, DDR4-COMP1, DDR4-RDIMM0, and DDR4-RDIMM1 memory on your board.

Figure 26. The COMP-O TabThis diagram applies to DK-DEV-AGI027RBES and DK-DEV-AGI027-RA.

The following sections describe controls on this tab.

Start

Initiates DDR4 memory transaction performance analysis.

Stop

Terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last clicked Start:

  • Write and Read performance bars: Show the percentage of the maximum theoretical data rate that the requested transactions are able to achieve.
  • Write (MBps) and Read (MBps): Show the number of bytes analyzed per second.
  • Data Bus: 72 bits (8 bits ECC) wide, reference clock is 33.33 MHz, and the frequency is 1333.33 MHz double data rate 2666.66 MT/s.

Test Control

  • Test Size: You can choose the size of the memory to test. The available options are 64 KB, 256 KB, 1 MB, 4 MB, 16 MB, 64 MB, 256 MB, 1 GB, 4 GB, and 8 GB (default).
  • Offset (Hex): You can define the memory start address to test.
  • Test Mode: Infinite Read and Write (default), Single Read and Write.
  • Test Pattern: PRBS (default), User Defined Constant, Walking ‘0’, Walking ‘1'.

Error Control

This control displays data errors detected during analysis and allows you to insert errors:

  • Detected Errors: Displays the number of data errors detected in the hardware.
  • Inserted Errors: Displays the number of errors inserted into the transaction stream.
  • Insert: Insert a one-word error into the transaction stream each time you click the button. Insert error is only enabled during transaction performance analysis.
  • Clear: Resets the Detected Errors counter and Inserted Errors counter to zeros.
Figure 27. The COMP-1 TabThis diagram applies to DK-DEV-AGI027RBES and DK-DEV-AGI027-RA. Same as DDR4-COMP0.
Figure 28. The RDIMM-0 TabThis diagram applies to DK-DEV-AGI027RBES and DK-DEV-AGI027-RA. Similar control functions to the DDR4-COMP0 tab, the total size is 16 GB.
Figure 29. The RDIMM-1 TabThis diagram applies to DK-DEV-AGI027RBES and DK-DEV-AGI027-RA. Same as RDIMM0.
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