Agilex™ 7 FPGA I-Series Development Kit User Guide

ID 683288
Date 5/31/2024
Public
Document Table of Contents

A.2. Agilex™ 7 FPGA I-Series

Agilex™ 7 FPGA I-Series 56 mm x 45 mm package:

  • Part Number: AGIB027R29A1E2VR0, AGIB027R29A1E2VR3, or AGIB027R29A1E1VB
  • 2957-Ball FBGA Package
  • 2.7M LEs
  • 8528 digital signal processing (DSP) blocks
  • 17056 18x19 Multipliers
  • LVDS pairs supporting 1.6 Gbps
  • 3x R-tile supporting PCIe* Gen5 x16 (32Gb/s) or CXL2 x16
  • 1x F tile transceiver supporting 56Gbps NRZ
  • Multiple channels to connect to external DDR4 memories
2 To activate the CXL hard IP and receive CXL soft R-Tile Wrapper and Soft Support logic, purchase or activation of a separate CXL IP license is required for proper use with the Quartus® Prime Design Software. Contact your local Intel® sales representative for pricing details. To activate a free-of-charge 30- or 60-days trial IP license, please contact your local Intel® sales representative.