Agilex™ 7 FPGA I-Series Development Kit User Guide

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ID 683288
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Applying Power to the Development Board 3.2. Default Settings 3.3. Performing Board Restore through Quartus® Prime Programmer 3.4. Generating a POF Image to Program the Flash 3.5. Programming the Generated POF Image 3.6. The Required SmartVID QSF Assignments to Compile a Design
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-board Power through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The RAM Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab
A. Development Kit Components x
A.1. Board Overview A.2. Agilex™ 7 FPGA I-Series A.3. PCIe* and CXL Interfaces A.4. MCIO Connector A.5. MCIO Cable Assembly Information A.6. Network Interfaces A.7. Port Controller A.8. FPGA Configuration A.9. Supported Configuration Modes A.10. Memory Interfaces A.11. I2C A.12. Clock Circuits A.13. System Power A.14. Temperature Monitoring A.15. Mechanical Requirements A.16. Board Thermal Requirements A.17. Board Operating Conditions A.18. Over Temperature Warning LED
A.13. System Power x
A.13.1. Power Guidelines A.13.2. Power Distribution System A.13.3. Power Sequence A.13.4. Power Measurement
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

1.2. Feature Summary

  • Agilex™ 7 FPGA I-Series (AGIB027) device in the 2957A BGA package
    • 0.8 VID-adjustable VCC core
    • R-Tile transceivers supporting PCIe* 5.0/CXL 2
    • F-Tile transceivers supporting 56 Gbps NRZ
  • FPGA configuration
    • Partial reconfiguration support
    • Configuration via Protocol (CvP) configuration support
    • Storage for two configuration images in flash (factory and user)
    • JTAG header for device programming
    • Built-in Intel® FPGA Download Cable II for device programming
  • Programmable clock sources
    • 156.25 MHz differential LVDS for F-Tile (QSFPDD)
    • 100.000 MHz HCSL for PCIe* and CXL (R-Tile)
    • 33.33 MHz differential LVDS for memory
    • 125 MHz configuration clock
    • 100 MHz differential LVDS for I/O banks
  • Transceiver interfaces
    • PCIe* /CXL x16 interface supporting the 5.0 end-point mode connected to a x16 PCIe* edge connector (gold edge fingers)
    • 2x standard QSFPDD optical module interfaces connected to the F-Tile transceivers
    • 1x PCIe* /CXL2 interface supporting CXL x16 or PCIe* x16 at 32 Gbps via MCIO connectors
  • Memory interfaces
    Note:

    DDR4 SDRAM memory on the board:

    • DK-DEV-AGI027-RA-B: 32Gb
    • DK-DEV-AGI027RES, DK-DEV-AGI027RBES, DK-DEV-AGI027R1BES, DK-DEV-AGI027-RA: 16 Gb
  • Communication ports
    • 2x QSFPDD optical interface port
    • JTAG header
    • USB (Micro USB) on-board Intel® FPGA Download Cable II
    • System I2C header
  • Buttons, switches, and LEDs
    • System reset push button
    • CPU reset push button
    • PCIe* reset push button
    • Four dedicated user LEDs
    • Link LED of each QSFP28 port to indicate the link and data transceiver
    • Two dedicated configuration status LEDs
  • Heatsink and Fan
    • Air-cooled heatsink assembly
    • Red over-temperature warning LED indicator
  • Power
    • PCIe* input power including required 2x4 auxiliary power connector
    • Blue power-on LED
    • On/off slide power switch for benchtop operation
    • On board power and temperature measurement circuitry
  • Mechanical
    • PCIe* standard height form factor (full height, 3/4 length, dual-width)
    • 4.376" x 10.0" board size
    • 2 slots height with heatsink
  • Operating environment
    • Maximum ambient temperature of 0–35°C
  • HPS dedicated interfaces (only available on selected board variants, refer to the Agilex™ 7 FPGA I-Series Development Kit Board Diagram (Power Solution 1 Board) figure)
    • JTAG connected to MAX® 10
    • I2C
    • UART connected to 3-Pin header
2 To activate the CXL hard IP and receive CXL soft R-Tile Wrapper and Soft Support logic, purchase or activation of a separate CXL IP license is required for proper use with the Quartus® Prime Design Software. Contact your local Altera sales representative for pricing details. To activate a free-of-charge 30- or 60-days trial IP license, contact your local Altera sales representative.
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