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Ixiasoft
A.1. Board Overview
A.2. Agilex™ 7 FPGA I-Series
A.3. PCIe* and CXL Interfaces
A.4. MCIO Connector
A.5. MCIO Cable Assembly Information
A.6. Network Interfaces
A.7. Port Controller
A.8. FPGA Configuration
A.9. Supported Configuration Modes
A.10. Memory Interfaces
A.11. I2C
A.12. Clock Circuits
A.13. System Power
A.14. Temperature Monitoring
A.15. Mechanical Requirements
A.16. Board Thermal Requirements
A.17. Board Operating Conditions
A.18. Over Temperature Warning LED
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Ixiasoft
A.12. Clock Circuits
All clocks are supplied by three on-board low-jitter programmable clock generator circuits. The following is the clock connection diagram to the Agilex™ 7 FPGA. For detailed clock connections, refer to the schematic.
- Si5391 provides most of the clocks to the Agilex™ 7 FPGA I-Series including reference clocks for memory interfaces, QSFP_DD, and the FPGA SDM/fabric core.
- Si52204 provides the dedicated reference clock as a local clock option for PCIe* Gen5 by selecting the inputs of a clock multiplex/buffer Si53307. Another input of the clock buffer is from PCIe* Edge connector as a system clock of PCIe* Gen5.
- Si510 provides a 50MHz clock to System MAX® 10 and power MAX® 10 devices.
Figure 42. Clock Connection Diagram