Agilex™ 7 FPGA I-Series Development Kit User Guide

ID 683288
Date 5/31/2024
Public
Document Table of Contents

A.12. Clock Circuits

All clocks are supplied by three on-board low-jitter programmable clock generator circuits. The following is the clock connection diagram to the Agilex™ 7 FPGA. For detailed clock connections, refer to the schematic.

  • Si5391 provides most of the clocks to the Agilex™ 7 FPGA I-Series including reference clocks for memory interfaces, QSFP_DD, and the FPGA SDM/fabric core.
  • Si52204 provides the dedicated reference clock as a local clock option for PCIe* Gen5 by selecting the inputs of a clock multiplex/buffer Si53307. Another input of the clock buffer is from PCIe* Edge connector as a system clock of PCIe* Gen5.
  • Si510 provides a 50MHz clock to System MAX® 10 and power MAX® 10 devices.
Figure 42. Clock Connection Diagram