Agilex™ 7 FPGA I-Series Development Kit User Guide

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ID 683288
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide A. Development Kits Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Box Contents 1.3. Operating Conditions
2. Getting Started x
2.1. About Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. About Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch Settings 3.3. How to Generate a POF Image to Program the Flash 3.4. How to Program the Generated POF Image 3.5. The Required SmartVID QSF Assignments to Compile a Design
3.2. Default Switch Settings x
3.2.1. Default Settings 3.2.2. Perform Board Restore through Quartus® Prime Programmer
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-board Clock through Clock Controller GUI 4.4. Monitor On-board Power through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The RAM Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab
A. Development Kits Components x
A.1. Board Overview A.2. Agilex™ 7 FPGA I-Series A.3. PCIe* and CXL Interfaces A.4. MCIO Connector A.5. MCIO Cable Assembly Information A.6. Network Interfaces A.7. Port Controller A.8. FPGA Configuration A.9. Supported Configuration Modes A.10. Memory Interfaces A.11. I2C A.12. Clock Circuits A.13. System Power A.14. Temperature Monitoring A.15. Mechanical Requirements A.16. Board Thermal Requirements A.17. Board Operating Conditions A.18. Over Temperature Warning LED
A.13. System Power x
A.13.1. Power Guidelines A.13.2. Power Distribution System A.13.3. Power Sequence A.13.4. Power Measurement
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide
A. Development Kits Components
B. Additional Information

1.1. Block Diagram

The demonstration board showcases the features of the Agilex™ 7 FPGA I-Series device in the F2957 FBGA package. These devices feature R-Tile transceivers with PCIe* Gen5 x16 and CXL 1 interfaces and F-Tile transceivers with 28G x8 or 56G x8 QSFPDD interfaces. The board supports two on-board DDR4 x72 with ECC channels. The board also features DDR4 DIMM support. Refer to the block diagrams for variations between board versions.

Figure 1.  Agilex™ 7 FPGA I-Series Development Kit Board DiagramThis diagram applies to DK-DEV-AGI027RES and DK-DEV-AGI027R1BES.
Figure 2.  Agilex™ 7 FPGA I-Series Development Kit Board DiagramThis diagram applies to DK-DEV-AGI027RBES and DK-DEV-AGI027-RA.

Feature Summary

  • Agilex™ 7 FPGA I-Series (AGIB027) device in the 2957A BGA package
    • 0.8 VID-adjustable VCC core
    • R-Tile transceivers supporting PCIe* Gen5/CXL1
    • F-Tile transceivers supporting 56 Gbps NRZ
  • FPGA configuration
    • Partial reconfiguration support
    • Configuration via Protocol (CvP) configuration support
    • Storage for two configuration images in flash (factory and user)
    • JTAG header for device programming
    • Built-in Intel® FPGA Download Cable II for device programming
  • Programmable clock sources
    • 156.25 MHz differential LVDS for F-Tile (QSFPDD)
    • 100.000 MHz HCSL for PCIe* and CXL (R-Tile)
    • 33.33 MHz differential LVDS for memory
    • 125 MHz configuration clock
    • 100 MHz differential LVDS for I/O banks
  • Transceiver interfaces
    • PCIe* /CXL x16 interface supporting the Gen5 end-point mode connected to a x16 PCIe* edge connector (gold edge fingers)
    • 2x standard QSFPDD optical module interfaces connected to the F-Tile transceivers
    • 1x PCIe* /CXL1 interface supporting CXL x16 or PCIe* x16 at 32 Gbps via MCIO connectors
  • Memory interfaces
    • Two on-board independent single rank DDR4 x72 (ECC) channels operating at 1333 MHz (DDR4-2666)
    • Two DIMM sockets which are either on a single memory channels (last two OPNs in Table 1) or each on independent channels (first two OPNs in Table 1). The DIMM supports DDR4 x72 (ECC) and can operate up to DDR-3200 (depending on the speed of the FPGA used).
  • Communication ports
    • 2x QSFPDD optical interface port
    • JTAG header
    • USB (Micro USB) on-board Intel® FPGA Download Cable II
    • System I2C header
  • Buttons, switches, and LEDs
    • System reset push button
    • CPU reset push button
    • PCIe* reset push button
    • Four dedicated user LEDs
    • Link LED of each QSFP28 port to indicate the link and data transceiver
    • Two dedicated configuration status LEDs
  • Heatsink and Fan
    • Air-cooled heatsink assembly
    • Red over-temperature warning LED indicator
  • Power
    • PCIe* input power including required 2x4 auxiliary power connector
    • Blue power-on LED
    • On/off slide power switch for benchtop operation
    • On board power and temperature measurement circuitry
  • Mechanical
    • PCIe* standard height form factor (full height, 3/4 length, dual-width)
    • 4.376" x 10.0" board size
    • 2 slots height with heatsink
  • Operating environment
    • Maximum ambient temperature of 0–35°C
  • HPS dedicated interfaces (only available on selected board variants, see Figure 2)
    • JTAG connected to MAX10
    • I2C
    • UART connected to 3-Pin header
1 To activate the CXL hard IP and receive CXL soft R-Tile Wrapper and Soft Support logic, purchase or activation of a separate CXL IP license is required for proper use with the Quartus® Prime Design Software. Contact your local Altera sales representative for pricing details. To activate a free-of-charge 30- or 60-days trial IP license, contact your local Altera sales representative.
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