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Ixiasoft
A.1. Board Overview
A.2. Agilex™ 7 FPGA I-Series
A.3. PCIe* and CXL Interfaces
A.4. MCIO Connector
A.5. MCIO Cable Assembly Information
A.6. Network Interfaces
A.7. Port Controller
A.8. FPGA Configuration
A.9. Supported Configuration Modes
A.10. Memory Interfaces
A.11. I2C
A.12. Clock Circuits
A.13. System Power
A.14. Temperature Monitoring
A.15. Mechanical Requirements
A.16. Board Thermal Requirements
A.17. Board Operating Conditions
A.18. Over Temperature Warning LED
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Ixiasoft
1.1. Block Diagram
The demonstration board showcases the features of the Agilex™ 7 FPGA I-Series device in the F2957 FBGA package. These devices feature R-Tile transceivers with PCIe* 5.0 x16 and CXL interfaces and F-Tile transceivers with 28G x8 or 56G x8 QSFPDD interfaces. The board supports two on-board DDR4 x72 with ECC channels. The board also features DDR4 DIMM support. Refer to the figures below for variations between board versions.
Figure 5. Agilex™ 7 FPGA I-Series Development Kit Board Diagram (Power Solution 2 Board)This diagram applies to DK-DEV-AGI027RBES, DK-DEV-AGI027-RA, and DK-DEV-AGI027-RA-B.
Figure 6. Agilex™ 7 FPGA I-Series Development Kit Board Diagram (Power Solution 1 Board)This diagram applies to DK-DEV-AGI027RES and DK-DEV-AGI027R1BES.
1 To activate the CXL hard IP and receive CXL soft R-Tile Wrapper and Soft Support logic, purchase or activation of a separate CXL IP license is required for proper use with the Quartus® Prime Design Software. Contact your local Altera sales representative for pricing details. To activate a free-of-charge 30- or 60-days trial IP license, contact your local Altera sales representative.