Agilex™ 7 FPGA I-Series Development Kit User Guide

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ID 683288
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide A. Development Kits Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Box Contents 1.3. Operating Conditions
2. Getting Started x
2.1. About Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. About Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch Settings 3.3. How to Generate a POF Image to Program the Flash 3.4. How to Program the Generated POF Image 3.5. The Required SmartVID QSF Assignments to Compile a Design
3.2. Default Switch Settings x
3.2.1. Default Settings 3.2.2. Perform Board Restore through Quartus® Prime Programmer
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-board Clock through Clock Controller GUI 4.4. Monitor On-board Power through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The RAM Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab
A. Development Kits Components x
A.1. Board Overview A.2. Agilex™ 7 FPGA I-Series A.3. PCIe* and CXL Interfaces A.4. MCIO Connector A.5. MCIO Cable Assembly Information A.6. Network Interfaces A.7. Port Controller A.8. FPGA Configuration A.9. Supported Configuration Modes A.10. Memory Interfaces A.11. I2C A.12. Clock Circuits A.13. System Power A.14. Temperature Monitoring A.15. Mechanical Requirements A.16. Board Thermal Requirements A.17. Board Operating Conditions A.18. Over Temperature Warning LED
A.13. System Power x
A.13.1. Power Guidelines A.13.2. Power Distribution System A.13.3. Power Sequence A.13.4. Power Measurement
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide
A. Development Kits Components
B. Additional Information

3.2.1. Default Settings

The Agilex™ 7 FPGA I-Series Development Kit ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the tables below to return to the factory settings before proceeding.

Table 4.  Factory Default Switch Settings for DK-DEV-AGI027RES and DK-DEV-AGI027R1BES
Note: X refers to Don't Care in this table.

For more information, refer to Board Overview.

Switch Default Position Function
SW1[1:4] ON/OFF/OFF/OFF

PCIe* PRSNT x1/x4/x8/x16 settings. Default = x16.

PCIe* PRSNT x16 PCIe* PRSNT x8 PCIe* PRSNT x4 PCIe* PRSNT x1
ON OFF OFF OFF
SW2[1:4] ON/OFF/OFF/X

Configuration mode setting bits.

Mode MSEL0 MSEL1 MSEL2 Reserved
JTAG OFF OFF OFF X
AVST x8 ON OFF OFF X
SW3[1:4] OFF/ON/ON/OFF
Type ON (Close) OFF (Open)
1: Si5391 Clock Enable Disable all clocks Enable all Clocks
2: CXL REFCLK Select CLK from CXL Connector On-board REFCLK
3: PCIe REFCLK Select CLK from PCIe* Connector On-board REFCLK
4: Si52204 Clock Enable Disable all clocks Enable all Clocks
SW4 OFF/OFF/OFF/OFF
Type ON (Close) OFF (Open)
1: FPGA I2C Enable MAIN I2C bus disable MAIN_I2C bus enable
2: FPGA I2C_2 Enable I2C2 Bus disable I2C2 Bus enable
3: Main PMBUS Enable CORE PMBUS disable CORE PMBUS enable
4: FPGA PMBUS Enable SDM_I2C Bus disable SDM_I2C Bus enable
SW5[1:4] OFF/OFF/OFF/X

On-board Intel® FPGA Download Cable II is the JTAG host when the external JTAG header (J10) is unoccupied.

Type ON OFF
1: JTAG input source PCIe EP Edge connector On-Board Intel® FPGA Download Cable II
2: FPGA Bypass Bypass FPGA FPGA in JTAG chain
3: MAX® 10 JTAG Select MAX® 10 JTAG Enable MAX® 10 JTAG Disable
4: Not used X X
SW6 ON/OFF

When the board is not in a PCIe* slot, it must be powered by an external power supply. The SW6 switch turns on the power of the board when it is at the ON position and turns off the power when it is at the OFF position.

When the board is in a PCIe* slot, the external and auxiliary power supplies must still be connected. The SW6 switch can be left at either the ON or OFF position. The board can only be powered on when both power sources are present.

Table 5.  Factory Default Switch Settings for DK-DEV-AGI027RBES and DK-DEV-AGI027-RA
Note: X refers to Don't Care in this table.

For more information, refer to Board Overview.

Switch Default Position Function
SW1[1:4] ON/OFF/OFF/OFF

PCIe* PRSNT x1/x4/x8/x16 settings. Default = x16.

PCIe* PRSNT x16 PCIe* PRSNT x8 PCIe* PRSNT x4 PCIe* PRSNT x1
ON OFF OFF OFF
SW2[1:4] ON/OFF/OFF/X

Configuration mode setting bits.

Mode MSEL0 MSEL1 MSEL2 Reserved
JTAG OFF OFF OFF X
AVST x8 ON OFF OFF X
SW3[1:4] OFF/OFF/OFF/OFF
Type ON (Close) OFF (Open)
1: Si5391 Clock Enable Disable all clocks Enable all Clocks
2: CXL REFCLK Select CLK from CXL Connector On-board REFCLK
3: PCIe REFCLK Select CLK from PCIe* Connector On-board REFCLK
4: Si52204 Clock Enable Disable all clocks Enable all Clocks
SW4[1:4] OFF/OFF/ON/OFF
Type ON (Close) OFF (Open)
1: FPGA I2C Enable MAIN I2C bus disable MAIN_I2C bus enable
2: FPGA I2C_2 Enable I2C2 Bus disable I2C2 Bus enable
3: Main PMBUS Enable CORE PMBUS disable CORE PMBUS enable
4: FPGA PMBUS Enable SDM_I2C Bus disable SDM_I2C Bus enable
SW8[1:4] OFF/OFF/OFF/X

On-board Intel® FPGA Download Cable II is the JTAG host when the external JTAG header (J10) is unoccupied.

Type ON OFF
1: JTAG input source PCIe EP Edge connector On-Board Intel® FPGA Download Cable II
2: FPGA Bypass Bypass FPGA FPGA in JTAG chain
3: MAX® 10 JTAG Select MAX® 10 JTAG Enable MAX® 10 JTAG Disable
4: Not used X X
SW6 ON/OFF

When the board is not in a PCIe* slot, it must be powered by an external power supply. The SW6 switch turns on the power of the board when it is at the ON position and turns off the power when it is at the OFF position.

When the board is in a PCIe* slot, the external and auxiliary power supplies must still be connected. The SW6 switch can be left at either the ON or OFF position. The board can only be powered on when both power sources are present.

Figure 4. SW1[1:4] Switch Setting
Figure 5. SW2[1:4] Switch Setting
Figure 6. SW3[1:4] Switch Setting
Figure 7. SW4[1:4] Switch Setting
Figure 8. SW5[1:4] Switch Setting
Figure 9. SW8[1:4] Switch Setting
Table 6.  Connectors on the Development Kit
Board Reference Type Description
J11 Auxiliary power connector For the external 12V auxiliary power supply or power adapter
J12 I2C/PMBus connector For accessing core power controller
J13 I2C connector For accessing to the main I2C1 bus
J3 QSFPDD_0 connector —
J4 QSFPDD_1 connector —
J8 USB connector For programming the FPGA using on-board Intel® FPGA Download Cable II
J10 External JTAG header For use with the external download cable
J1 DIMM A connector DDR4 Dual DIMM A
J2 DIMM B connector DDR4 Dual DIMM B
J5 PCIe* x16 Gold Finger —
J6, J7 CXL/ PCIe* connectors For connecting the external CXL/ PCIe* MCIO cables
J24 Fan connector For connecting to the heatsink cooling fan
Table 7.  LEDs on the Development Kit
Board Reference Type Description
D1 QSFPDD_0 Link/Activity LED Green LED - User defined
D2 QSFPDD_0 Link/Activity LED (Dual color)

Yellow LED – User defined

Green LED - User defined
D3 QSFPDD_1 Link/Activity LED Green LED - User defined
D4 QSFPDD_1 Link/Activity LED (Dual color)

Yellow LED – User defined

Green LED - User defined
D5 USER LED 0 Green LED for USER LED 0
D7 USER LED 1 Green LED for USER LED 1
D8 USER LED 2 Green LED for USER LED 2
D10 USER LED 3 Green LED for USER LED 3
D6 POWER GOOD LED

Blue LED:

  • ON: All powers are good.
  • OFF: Power failure
D11 CONFIG DONE LED

Green LED:

  • ON: FPGA configuration successful
  • OFF: FPGA configuration failed
D9 Over Temp LED

Red LED:

  • ON: FPGA over temperature condition
Table 8.  Push-Buttons on the Development Kit
Board Reference Type Description
S1 CPU Reset Push to reset FPGA
S2 PCIe* Reset Push to reset PCIe* bus on MCIO connectors (J6 and J7)
S3 CXL Reset Push to reset CXL bus on MCIO connectors (J6 and J7)
S4 USB PHY Reset Push to reset on-board USB PHY
S5 QSFPDD_1 Reset Push to reset F-tile for QSFPDD_1 port
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