Agilex™ 7 FPGA I-Series Development Kit User Guide

Download PDF
ID 683288
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide A. Development Kits Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Box Contents 1.3. Operating Conditions
2. Getting Started x
2.1. About Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. About Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch Settings 3.3. How to Generate a POF Image to Program the Flash 3.4. How to Program the Generated POF Image 3.5. The Required SmartVID QSF Assignments to Compile a Design
3.2. Default Switch Settings x
3.2.1. Default Settings 3.2.2. Perform Board Restore through Quartus® Prime Programmer
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-board Clock through Clock Controller GUI 4.4. Monitor On-board Power through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The RAM Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab
A. Development Kits Components x
A.1. Board Overview A.2. Agilex™ 7 FPGA I-Series A.3. PCIe* and CXL Interfaces A.4. MCIO Connector A.5. MCIO Cable Assembly Information A.6. Network Interfaces A.7. Port Controller A.8. FPGA Configuration A.9. Supported Configuration Modes A.10. Memory Interfaces A.11. I2C A.12. Clock Circuits A.13. System Power A.14. Temperature Monitoring A.15. Mechanical Requirements A.16. Board Thermal Requirements A.17. Board Operating Conditions A.18. Over Temperature Warning LED
A.13. System Power x
A.13.1. Power Guidelines A.13.2. Power Distribution System A.13.3. Power Sequence A.13.4. Power Measurement
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide
A. Development Kits Components
B. Additional Information

A.10. Memory Interfaces

This memory information applies to DK-DEV-AGI027RES and DK-DEV-AGI027R1BES.

Three independent memory interfaces are supported: Two independent on-board DDR4 and one dual DIMM sockets for DDR4.

  • The on-board DDR4 uses five 16 Gb DDR4 single rank devices connecting to Bank 2B, 2E for memory component channel 0 and bank 2C, 2F for memory component channel 1. The total memory size of each channel is 16 GB running at 1200 MHz.
  • The two 288-pin DIMM sockets interface to bank 3C, 3D for Dual DIMM memory. These sockets accept DDR4 module. These DIMM support dual rank at frequency 1333 MHZ 16 GB per channel, and single rank at 1333 MHZ 8 GB per channel.
    • Some board re-work is required for using DIMM sockets in 2-DPC configuration or different kinds of DDR4 modules. For more details of the resistor connections required to be present for the type of configuration used, refer to board schematic table.
  • The 1.2 V DDR power supply is designed to support up to 12 A currents to the two DIMM slots. This is sufficient to support 64 GB DIMMs in both slots (128 GB in total). If higher capacity DIMM has to be supported, the DDR power supply design must be updated to use a higher rated 1.2 V voltage regulator based on the current requirement of the DIMMs.
This memory information applies to DK-DEV-AGI027RBES and DK-DEV-AGI027-RA.
  • The on-board DDR4 uses five 16 Gb DDR4 single rank devices connecting to Bank 3A, 3B for memory component channel 0 and bank 3C, 3D for memory component channel 1. The total memory size of each channel is 16 GB running at 1200 MHz.
  • The two 288-pin DIMM sockets interface to bank 2B, 2E for Dual DIMM memory channel 2 and bank 2F, 2C for Dual DIMM memory channel 1. These sockets accept DDR4 modules. These DIMM support dual rank at frequency 1200 MHZ 16 GB per channel, and single rank at 1200 MHZ 8 GB per channel.
  • The 1.2 V DDR power supply is designed to support up to 12 A currents to the two DIMM slots. This is sufficient to support 64 GB DIMMs in both slots (128 GB in total). If higher capacity DIMM has to be supported, the DDR power supply design must be updated to use a higher rated 1.2 V voltage regulator based on the current requirement of the DIMMs.
Level Two Title