Developer Guide

Intel oneAPI FPGA Handbook

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Date 2/07/2024
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Document Table of Contents
Document Table of Contents x
Intel® oneAPI FPGA Handbook Introduction To FPGA Design Concepts Intel oneAPI FPGA Development Defining a Kernel for FPGAs Debugging and Verifying Your Design Analyzing Your Design Optimizing Your Kernel Optimizing Your Host Application Integrating Your RTL IP Core Into a System RTL IP Core Kernel Interfaces Loops Pipes Data Types and Arithmetic Operations Parallelism Memories and Memory Operations Libraries Additional FPGA Acceleration Flow Considerations Additional SYCL* HLS Flow Considerations FPGA Optimization Flags, Attributes, Pragmas, and Extensions Quick Reference Additional Information Document Revision History for the Intel oneAPI FPGA Handbook Notices and Disclaimers
Introduction To FPGA Design Concepts x
FPGA Architecture Overview Concepts of FPGA Hardware Design How Source Code Becomes a Custom Hardware Datapath
How Source Code Becomes a Custom Hardware Datapath x
Mapping Source Code Instructions to Hardware Scheduling Mapping Parallelism Models to FPGA Hardware Memory Types
Intel oneAPI FPGA Development x
FPGA Flow Terminology Intel oneAPI FPGA Development Flow Types of SYCL* FPGA Compilation FPGA Compilation Flags FPGA Workflows in IDEs
Types of SYCL* FPGA Compilation x
Separating Device and Host Code Compilation
Defining a Kernel for FPGAs x
Suggested Kernel Coding Styles Single Work-Item Kernels
Single Work-Item Kernels x
Single Work-item Kernel Design Guidelines Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
Strategies for Inferring the Accumulator
Debugging and Verifying Your Design x
Device Selectors for FPGA printf Command Restrictions Emulate and Debug Your Design Evaluate Your Kernel Through Simulation
Emulate and Debug Your Design x
Emulator Environment Variables Compile and Emulate Your Design Limitations of the Emulator Troubleshooting Discrepancies in Hardware and Emulator Results Emulator Known Issues
Evaluate Your Kernel Through Simulation x
Debug During Verification Simulation Prerequisites Installing the Questa*-Intel FPGA Edition Software Set Up the Simulation Environment Compile a Kernel for Simulation Simulate Your Kernel Viewing Simulation Waveforms Troubleshooting Simulator Issues
Analyzing Your Design x
Analyze the FPGA Early Image Analyze the FPGA Image Review the FPGA Optimization Report Quartus (Static) Summary Intel® FPGA Dynamic Profiler for DPC++ System-level Profiling Using the Intercept Layer for OpenCL™ Applications
Review the FPGA Optimization Report x
Loop Analysis Bottlenecks Viewer Area Estimates System Viewer Kernel Memory Viewer Schedule Viewer Access HLD FPGA Reports in JSON Format
Quartus (Static) Summary x
Timing Failures
Intel® FPGA Dynamic Profiler for DPC++ x
Measure Kernel Performance Instrument the Kernel Pipeline with Performance Counters (-Xsprofile) Obtain Profiling Data During Run Time Reduce Area Resource Use While Profiling Profiler Analyses of Example SYCL* Design Scenarios Limitations
Obtain Profiling Data During Run Time x
Invoke the Profiler Runtime Wrapper to Obtain Profiling Data Use Intel® VTune™ Profiler
Use Intel® VTune™ Profiler x
Interpret Performance Counter Data
System-level Profiling Using the Intercept Layer for OpenCL™ Applications x
Set Up the Intercept Layer for OpenCL™ Applications
Optimizing Your Host Application x
Throughput Resource Use Multi-Threaded Host Application Utilizing Hardware Kernel Invocation Queue Double Buffering Host Utilizing Kernel Invocation Queue N-Way Buffering to Overlap Kernel Execution Prepinning Memory Simple Host-Device Streaming Buffered Host-Device Streaming
Double Buffering Host Utilizing Kernel Invocation Queue x
Applying Double-Buffering Using the Intercept Layer for OpenCL™ Applications
Integrating Your RTL IP Core Into a System x
Synthesize Your RTL IP Core with Intel Quartus Prime Software Add RTL IP Component into a Platform Designer System Add an RTL IP Component into an Intel® Quartus® Prime Project Encrypt RTL IP Components for Distribution
RTL IP Core Kernel Interfaces x
Kernel Argument Interfaces Memory-Mapped (MM) Agent Kernel Invocation Interface Ready/Valid Handshaking Kernel Invocation Interface Memory-Mapped Host Interfaces
Memory-Mapped Host Interfaces x
Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the annotated_arg Class Memory-Mapped Host Interfaces Using Accessors (Deprecated) Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the mmhost Macro
Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the annotated_arg Class x
Buffer Locations in Memory-Mapped Host Interfaces The annotated_arg Template Class Recommended Method for Annotating struct Data Types sycl::ext::intel::experimental::conduit Declaration sycl::ext::intel::experimental::register_map Declaration sycl::ext::intel::experimental::stable Declaration sycl::ext::intel::experimental::buffer_location Property sycl::ext::intel::experimental::dwidth Property sycl::ext::intel::experimental::awidth Property sycl::ext::intel::experimental::latency Property sycl::ext::intel::experimental::maxburst Property sycl::ext::intel::experimental::alignment Property sycl::ext::intel::experimental::read_write_mode Property
Loops x
Refactor the Loop-Carried Data Dependency Relax Loop-Carried Dependency Transfer Loop-Carried Dependency to Local Memory Minimize the Memory Dependencies for Loop Pipelining Unroll Loops Fuse Loops to Reduce Overhead and Improve Performance Optimize Loops With Loop Speculation Remove Loop Bottlenecks Improve fMAX/II with Shannonization Optimize Inner Loop Throughput Improve Loop Performance by Caching Data in On-Chip Memory
Pipes x
Host Pipes Pipes Extension Emulate Applications with a Pipe That Reads or Writes to an I/O Pipe
Host Pipes x
Host Pipe Declaration Host Pipe API Host Pipes RTL Interfaces
Pipes Extension x
Key Properties of a Pipe Accessing Pipes The pipe Class and its Use I/O Pipes Characteristics of Pipes Restrictions of Pipes Guidelines for Designing Pipes The atomic_fence Function and Pipes
Data Types and Arithmetic Operations x
Optimize Floating-point Operation Avoid Expensive Functions Variable-Precision Data Type Support
Variable-Precision Data Type Support x
Advantages and Limitations of Variable Precision Data Types Declare and Use the AC Data Types
Declare and Use the AC Data Types x
Declare the ac_int Data Type Declare the ac_fixed Data Type Declare the ac_complex Data Type Declare the ap_float Data Type
Declare the ap_float Data Type x
Conversion Rules for the ap_float Data Type Operations with Explicit Precision Controls Comparison Operators Additional ap_float Functions Additional Data Types Provided by the ap_float.hpp Header File Quality of Results and the ap_float Data Type
Parallelism x
Pipelined Kernels NDRange Kernels Asynchronous Parallelism Within Kernels (task_sequence)
Pipelined Kernels x
Stable Arguments
Asynchronous Parallelism Within Kernels (task_sequence) x
Task Functions task_sequence Use Cases
Memories and Memory Operations x
The device_global Extension (Beta) Memory Accesses Kernel Variable Accesses
Memory Accesses x
Load-Store Units Global Memory Accesses Optimization Perform Kernel Computations Using Local or Private Memory Local and Private Memory Accesses Optimization Annotating Unified Shared Memory Pointers Zero-Copy Memory Access Additional Recommendations
Load-Store Units x
Load-Store Unit Styles Load-Store Unit Modifiers Load-Store Unit Controls
Global Memory Accesses Optimization x
Global Memory Bandwidth Use Calculation Manual Partition of Global Memory Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) Partitioning Buffers Across Memory Channels of the Same Memory Type Ignoring Dependencies Between Accessor Arguments Contiguous Memory Accesses Static Memory Coalescing
Libraries x
Use SYCL Shared Library With Third-Party Applications Use of RTL Libraries for FPGA Object Manifest File Syntax of an RTL Library Restrictions and Limitations in RTL Support Intel® Stratix® 10 and Intel Agilex® 7 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Libraries Stall-Free RTL
Additional FPGA Acceleration Flow Considerations x
FPGA-CPU Interaction FPGA BSPs and Boards Targeting Multiple Homogeneous FPGA Devices Targeting Multiple Platforms Split Kernel into Multiple FPGA Images (Linux only)
FPGA BSPs and Boards x
FPGA Board Initialization Obtain FPGA Hardware Image Information Extracting the FPGA Hardware Configuration (.aocx) File from a Multiarchitecture Binary File
Additional SYCL* HLS Flow Considerations x
IP Component Reset Behavior
FPGA Optimization Flags, Attributes, Pragmas, and Extensions x
Optimization Flags Optimization Targets Kernel Variables Kernel Attributes Memory Attributes Loop Directives Floating-Point Pragmas Latency Controls (Beta)
Optimization Flags x
Specify Schedule FMAX Target for Kernels (-Xsclock=<clock target>) Create a 2xclock Interface (-Xsuse-2xclock) Disable Burst-Interleaving of Global Memory (-Xsno-interleaving=<global_memory_name>) Force Ring Interconnect for Global Memory (-Xsglobal-ring) Force a Single Store Ring to Reduce Area (-Xsforce-single-store-ring) Force Fewer Read Data Reorder Units to Reduce Area (-Xsnum-reorder) Disable Hardware Kernel Invocation Queue (-Xsno-hardware-kernel-invocation-queue) Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking) Disable Automatic Fusion of Loops (-Xsdisable-auto-loop-fusion) Fuse Adjacent Loops With Unequal Trip Counts (-Xsenable-unequal-tc-fusion) Pipeline Loops in Non-task Kernels (-Xsauto-pipeline) Control Semantics of Floating-Point Operations (-fp-model=<value>) Modify the Rounding Mode of Floating-point Operations (-Xsrounding=<rounding_type>) Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>) Enable the Read-Only Cache for Read-Only Accessors (-Xsread-only-cache-size=<N>) Control Hardware Implementation of the Supported Data Types and Math Operations (-Xsdsp-mode=<option>) Generate Register Map Wrapper (-Xsregister-map-wrapper-type)
Optimization Targets x
Minimum Latency Flow Balanced Throughput-Area Trade-Offs Flow
Kernel Attributes x
Specify Schedule FMAX Target for Kernels Specify a Workgroup Size Specify Number of SIMD Work Items Omit Hardware that Generates and Dispatches Kernel IDs Omit Hardware to Support the no_global_work_offset Attribute in parallel_for Kernels Reduce Kernel Area and Latency
Loop Directives x
disable_loop_pipelining Attribute initiation_interval Attribute ivdep Attribute loop_coalesce Attribute max_concurrency Attribute max_interleaving Attribute speculated_iterations Attribute unroll Pragma Loop Fuse Functions and nofusion Attribute max_reinvocation_delay Attribute (Beta)
Quick Reference x
Algorithmic C Data Types Floating Point Pragmas FPGA Accessor Properties FPGA Extensions FPGA Kernel Attributes FPGA Local Memory Function Latency Control Properties (Beta) FPGA LSU Controls FPGA Loop Directives FPGA Memory Attributes FPGA Optimization Flags Pipe API
Intel® oneAPI FPGA Handbook
Introduction To FPGA Design Concepts
Intel oneAPI FPGA Development
Defining a Kernel for FPGAs
Debugging and Verifying Your Design
Analyzing Your Design
Optimizing Your Kernel
Optimizing Your Host Application
Integrating Your RTL IP Core Into a System
RTL IP Core Kernel Interfaces
Loops
Pipes
Data Types and Arithmetic Operations
Parallelism
Memories and Memory Operations
Libraries
Additional FPGA Acceleration Flow Considerations
Additional SYCL* HLS Flow Considerations
FPGA Optimization Flags, Attributes, Pragmas, and Extensions
Quick Reference
Additional Information
Document Revision History for the Intel oneAPI FPGA Handbook
Notices and Disclaimers

The annotated_arg Template Class

Use the annotated_arg template class to annotate your kernel arguments with properties that direct the compiler to customize the kernel argument interface.

The annotated_arg template class is provided in the fpga_extension.hpp header file and uses the sycl::ext::intel::experimental namespace. To use the annotated_arg template class, use the following declarations in your code:

#include <sycl/ext/intel/fpga_extension.hpp>
using namespace sycl::ext::intel::experimental;
using namespace sycl::ext::oneapi::experimental;

The annotated_arg template class has the following syntax:

annotated_arg<data type,decltype(properties { (conduit | register_map),
                                                [stable,]
                                                [buffer_location<id>,]
                                                [dwidth<data_bus_width,]
                                                [awidth<address_bus_wdith>,]
                                                [latency<value>,]
                                                [maxburst<value>,]
                                                [alignment<value>,]
                                                [read_write_mode<mode>] } ) >

When passing pointers to a SYCL* kernel with the annotated_arg template class, the pointer needs memory allocated using USM memory allocation APIs such as malloc_shared or alligned_alloc_shared.

RESTRICTION:
  • For aggregate data types (like struct), the annotated_arg template class does not support the dot (.) and the arrow (->) member-access operators. You must use an explicit or implicit conversion to the underlying date type before accessing the members of the aggregate data type.
  • The annotated_arg template class does not support using variable-precision data types (like ac_int) operations (like addition, multiplication...) directly. If you want to use the annotated_arg template class with a variable-precision data type, you must cast the annotated_arg object to the underlying data type object and perform operations on that object directly. For more details, refer to Recommended Method for Annotating struct Data Types.

Recommended Method for Annotating struct Data Types

When you annotate struct data types, create a local variable that stores the kernel argument of struct type so that member functions and data members of the struct types can be accessed directly.

The following example code demonstrates how to annotate a kernel argument of ac_int data type:

using ac_int_type = ac_int<17, true>;

struct MyIP {
    annotated_arg<ac_int_type, decltype(properties{conduit})> a;
    annotated_arg<ac_int_type, decltype(properties{conduit})> b;
    annotated_arg<int*, decltype(properties{conduit})> c;
    void operator()() const {
        // Make local variables of the struct type before using them
        ac_int_type n1 = a;
        ac_int_type n2 = b;
        *c = n1 + n2;
    }
};

The following example code demonstrates how to annotate a kernel argument of struct data type:

struct DataT{
    float f1;
    float f2;
};

struct MyIP {
    annotated_arg<DataT, decltype(properties{conduit})> inp;
    annotated_arg<float*, decltype(properties{conduit})> sum;
    void operator()() const {
        // Make local variables of the struct type from the kernel argument
        // before using the kernel argument
        DataT data = inp;
        // This allows access to struct members with the 'dot' operator
        *c = data.f1 + data.f2;
    }
};

The annotated_arg Template Class Properties Summary
Template Object or Parameter Description Valid Values
Interface Type Properties
sycl::ext::intel::experimental::conduit Create a dedicated input conduit on the kernel. N/A
sycl::ext::intel::experimental::register_map Creates an input register map for the input instead of a dedicated input port. N/A
sycl::ext::intel::experimental::stable Specifies that the input to the kernel does not change between pipelined invocations of the kernel.

The input can change after all active kernel invocations have finished.

 N/A
Pointer Kernel Argument Properties
sycl::ext::intel::experimental::buffer_location The global memory identifier for the pointer interface.

To use any of the other Avalon® MM Host interface properties, you must also specify the buffer_location property.

 N/A
sycl::ext::intel::experimental::dwidth The width of the memory-mapped data bus in bits 8, 16, 32, 64, 128, 256, 512, or 1024

Default: 64
sycl::ext::intel::experimental::awidth The width of the memory-mapped address bus in bits. Integer 11 – 41

Default: 41
sycl::ext::intel::experimental::latency The guaranteed latency from when a read command exits the kernel until the external memory returns valid read data. Non-negative integer value

Default: 1
sycl::ext::intel::experimental::maxburst The maximum number of data transfers that can associate with a read or write transaction. Integer 1 – 1024
sycl::ext::intel::experimental::alignment The alignment of the base pointer address in bytes. See description
sycl::ext::intel::experimental::read_write_mode The port direction of the interface. read_write, read, or write

Default: read_write

sycl::ext::intel::experimental::conduit Declaration

Syntax
sycl::ext::intel::experimental:conduit
Description
Directs the compiler to create a dedicated input conduit on the kernel for the kernel arguments. That input conduit is associated with the kernel start and busy signals.

This parameter is mutually exclusive with the sycl::ext::intel::experimental::register_map declaration.

sycl::ext::intel::experimental::register_map Declaration

Syntax
sycl::ext::intel::experimental::register_map
Description
Directs the compiler to create a register map to store the input.

This declaration is mutually exclusive with the sycl::ext::intel::experimental:conduit declaration.

sycl::ext::intel::experimental::stable Declaration

Syntax
sycl::ext::intel::experimental::stable
Description

While the SYCL* software model makes kernel arguments read-only, the RTL IP component generated by the compiler can be plugged into external systems where kernel arguments can change while the kernel executes.

This property specifies that the input to the kernel does not change between pipelined invocations of the kernel. The input can still change after all active kernel invocations have finished.

If the input changes while the pipelined kernel invocations are executing, the behavior is undefined.

sycl::ext::intel::experimental::buffer_location Property

Syntax

template <unsigned id>
sycl::ext::intel::experimental::buffer_location<id>

Description
Specifies a global memory identifier for the pointer interface. You must specify this argument to use any of the other Avalon® MM Host interface properties. Pointers with this argument specified are often referred to as annotated pointers.

Each unique ID results in a separate Avalon® MM Host interface on your RTP IP core. All hosts with the same address space are arbitrated within the kernel to a single interface. As such, these hosts must share the same template parameters that describe the interface.

If this property is not specified, the pointer argument is considered to be an unannotated pointer.

If you mix annotated pointers (that is, pointers with specified buffer locations) and unannotated pointers, ensure that you review Mixing Annotated and Unannotated Pointers in Your Kernel to understand the implications of mixing pointer types.

If all pointers in your kernel are unannotated, the compiler infers an Avalon® MM Host interface with a buffer location ID of 0.

IMPORTANT:
The caller is responsible for ensuring the correct buffer location is specified; otherwise, functional failures might occur. If you specify a buffer_location property on your kernel argument, specify the same buffer location on the USM allocation API call that allocates memory on the test bench (that is, the host code).

RESTRICTION:
If you use annotated pointers, you cannot mix sycl::accessor and annotated_arg kernel arguments.

sycl::ext::intel::experimental::dwidth Property

Syntax

template <unsigned width>
sycl::ext::intel::experimental::dwidth<width>

Valid Values
8, 16, 32, 64, 128, 256, 512, or 1024
Default Value
64
Description
The width of the memory-mapped data bus in bits.

To specify the dwidth property, you must also specify the buffer_location property.

sycl::ext::intel::experimental::awidth Property

Syntax

template <unsigned width>
sycl::ext::intel::experimental::awidth<width>

Valid Values
Integer value in the range 11-41
Default Value
41
Description
The width of the address bus. This value affects only the width of the Avalon® MM host interface.

RESTRICTION:
The lowest-numbered buffer location must have a minimum address width of 11-bits (awidth<11>). There is no minimum width for higher-numbered buffer locations.

To specify the awidth property, you must also specify the buffer_location property.

sycl::ext::intel::experimental::latency Property

Syntax

template <unsigned value>
sycl::ext::intel::experimental::latency<value>

Valid Values
Non-negative integer value
Default Value
1
Description
The guaranteed latency from when a read command exits the kernel to when the external memory returns valid read data.

If this latency is variable (such as when accessing DRAM), set it to 0.

To specify the latency property, you must also specify the buffer_location property.

sycl::ext::intel::experimental::maxburst Property

Syntax

template <unsigned value>
sycl::ext::intel::experimental::maxburst<value>

Valid Values
Integer value in the range 1 – 1024
Default Value
1
Description
The maximum number of data transfers that can associate with a read or write transaction. This value controls the width of the burstcount signal.

For fixed latency interfaces, this value must be set to 1.

For more details, review information about burst signals and the burstcount signal role in "Avalon Memory-Mapped Interface Signal Roles" in Avalon Interface Specifications.

To specify the maxburst property, you must also specify the buffer_location property and set the latency property to 0 (latency<0>).

sycl::ext::intel::experimental::alignment Property

Syntax

template <unsigned value>
sycl::ext::intel::experimental::alignment<value>

Valid Values
Integer value greater than the alignment of the data type
Default Value
1
Description
The alignment of the base pointer address in bytes.

The compiler uses this information to determine how many simultaneous loads and stores this pointer can permit.

For example, if you have a bus with 4 32-bit integers on it, you should use sycl::ext::intel::experimental::dwidth<128> (bits) and sycl::ext::intel::experimental::align<16> (bytes). This means that up to 16 contiguous bytes (or 4 32-bit integers) can be loaded or stored as a coalesced memory word per clock cycle.

IMPORTANT:
The caller is responsible for aligning the data to the set value for the align argument; otherwise, functional failures might occur. If you specify this property, ensure that you specify the same alignment value the following locations:
  • The sycl::ext::intel::experimental::alignment<value> property
  • The alignment argument of the aligned_malloc_shared template function in your host code. For example, 
    aligned_malloc_shared<int>(value, 1, q );

sycl::ext::intel::experimental::read_write_mode Property

Syntax

template <unsigned mode>
sycl::ext::intel::experimental::read_write_mode<value>

Valid Values
read_write, read, or write
Default Value
readwrite
Description
The port direction of the memory interface associated with the input pointer. Only the relevant Avalon host signals are generated.

The available modes are as follows:

  • read_write: The interface can used for read-write operations. You can also specify the sycl::ext::intel::experimental::read_write_mode_readwrite property to enable this mode.
  • read: The interface is read-only. It be used only for read operations. You can also specify the sycl::ext::intel::experimental::read_write_mode_read property to enable this mode.
  • write: The interface is write-only. It can be used only for write operations. You can also specify the sycl::ext::intel::experimental::read_write_mode_write property to enable this mode.

To specify the read_write_mode property, you must also specify the buffer_location property.

Parent topic: Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the annotated_arg Class
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