Developer Guide

Intel oneAPI FPGA Handbook

ID 785441
Date 2/07/2024
Public

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Document Table of Contents

FPGA Optimization Flags

The following table summarizes FPGA optimization flags:

FPGA Optimization Flags

Flags

Description

Example

-Xsclock=<clock target in Hz/KHz/MHz/GHz or s/ms/us/ns/ps>

Schedules fMAX target for kernels.

icpx -fsycl -fintelfpga –Xshardware –Xsclock=<clock target> <source_file>.cpp
-Xsuse-2xclock Explicitly creates a 2xclock interface for the given design. icpx -fsycl -fintelfpga –Xshardware -Xsuse-2xclock source_file.cpp
-Xsno-interleaving=<global_memory_name>

Disables burst-interleaving for all global memory banks of the same type and manages them manually

icpx -fsycl -fintelfpga -Xshardware <source_file>.cpp-Xsno-interleaving=DDR
-Xsglobal-ring

Forces ring interconnect for global memory.

icpx -fsycl -fintelfpga -Xshardware -Xsglobal-ring <source_file>.cpp
-Xsforce-single-store-ring

Narrows the interconnect to save area while limiting write-only throughput to one bank's worth.

icpx -fsycl -fintelfpga -Xshardware -Xsforce-single-store-ring <source_file>.cpp
-Xsnum-reorder

Narrows the interconnect to save area while reducing read-only throughput.

icpx -fsycl -fintelfpga -Xshardware -Xsnum-reorder=1 <source_file>.cpp
-Xsno-hardware-kernel-invocation-queue

Reduces kernel area use by removing kernel invocation queue in SYCL* kernel.

icpx -fsycl -fintelfpga -Xshardware -Xsno-hardware-kernel-invocation-queue <source_file>.cpp
-Xshyper-optimized-handshaking=<auto|off>

Modifies the handshaking protocol used in certain areas of the design

icpx -fsycl -fintelfpga -Xshardware -Xshyper-optimized-handshaking=auto <source_file>.cpp
icpx -fsycl -fintelfpga -Xshardware -Xshyper-optimized-handshaking=off <source_file>.cpp
-Xsdisable-auto-loop-fusion

Disables the automatic fusion of loops when compiling the design.

icpx -fsycl -fintelfpga -Xshardware -Xsdisable-auto-loop-fusion <source_file>.cpp
-Xsenable-unequal-tc-fusion

Fuses adjacent loops with unequal trip counts into a single loop without affecting either loop's functionality.

icpx -fsycl -fintelfpga -Xshardware -Xsenable-unequal-tc-fusion <source_file>.cpp
-Xsauto-pipeline

Pipelines loops in non-task (parallel_for) kernels.

icpx -fsycl -fintelfpga –Xshardware -Xsauto-pipeline <source_file>.cpp
-fp-model=<value>

Controls the semantics of floating-point operations.

icpx -fsycl -fintelfpga -Xshardware -fp-model=<value> <source_file>.cpp
-Xsrounding=<rounding_type> Modifies the rounding mode of floating-point elementary operations in your design. icpx -fsycl -fintelfpga -Xshardware -Xsrounding=ieee <source_file>.cpp

icpx -fsycl -fintelfpga -Xshardware -Xsrounding=faithful <source_file>.cpp

-Xssfc-exit-fifo-type=<default|zero-latency|low-latency> Globally controls exit FIFO latency of stall-free clusters using the specified exit FIFO type. icpx -fsycl -fintelfpga -Xshardware -Xssfc-exit-fifo-type=zero-latency <source_file>.cpp
-Xsread-only-cache-size=<N>

Enables read-only cache and sets its size to <N> bytes.

icpx -fsycl -fintelfpga -Xshardware -Xsread-only-cache-size=<N><source_file>.cpp
-Xsdsp-mode=[default|prefer-dsp|prefer-softlogic] Controls the hardware implementation of the supported data types and math functions of all kernels in your source code. icpx -fsycl -fintelfpga –Xshardware -Xsdsp-mode=<option> <source_file>.cpp
-Xsregister-map-wrapper-type Generates a ring-like wrapper structure to connect all register map interfaces for different kernels inside an IP core. icpx -fsycl -fintelfpga –Xshardware -Xsregister-map-wrapper-type=<default|high-fmax|low-latency> source_file.cpp