Developer Guide

Intel oneAPI FPGA Handbook

ID 785441
Date 2/07/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

Intel oneAPI FPGA Development

The Intel® oneAPI Base Toolkit can generate the following types of outputs for FGPA devices:

  • Multiarchitecture binary (also known as a fat binary)

    A multiarchitecture binary contains both host code and FPGA device code.

    Multiarchitecture binaries require an FPGA acceleration board and the some aspects of your FPGA code are constrained by the capabilities provided by the board support package (BSP). For more information about BSPs and boards, refer to FPGA BSPs and Boards.

    The flow for creating a multiarchitecture binary is referred to as the FPGA acceleration flow. It might also occasionally be referred to as the full-stack flow.

  • RTL IP core

    An RTL IP core is ready to integrate into your overall FPGA application. Use Intel®Quartus® Prime Platform Designer to integrate the IP core into your design.

    In an RTL IP core, the FPGA capabilities you can access are not constrained by a BSP. However, you are responsible for more parts of the IP design than when generating a multiarchitecture binary.

    The flow for creating an RTL IP core is called the SYCL high-level synthesis (HLS) flow or just HLS flow. It might also occasionally be referred to as the IP authoring flow.