Developer Guide

Intel oneAPI FPGA Handbook

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Date 2/07/2024
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Document Table of Contents
Document Table of Contents x
Intel® oneAPI FPGA Handbook Introduction To FPGA Design Concepts Intel oneAPI FPGA Development Defining a Kernel for FPGAs Debugging and Verifying Your Design Analyzing Your Design Optimizing Your Kernel Optimizing Your Host Application Integrating Your RTL IP Core Into a System RTL IP Core Kernel Interfaces Loops Pipes Data Types and Arithmetic Operations Parallelism Memories and Memory Operations Libraries Additional FPGA Acceleration Flow Considerations Additional SYCL* HLS Flow Considerations FPGA Optimization Flags, Attributes, Pragmas, and Extensions Quick Reference Additional Information Document Revision History for the Intel oneAPI FPGA Handbook Notices and Disclaimers
Introduction To FPGA Design Concepts x
FPGA Architecture Overview Concepts of FPGA Hardware Design How Source Code Becomes a Custom Hardware Datapath
How Source Code Becomes a Custom Hardware Datapath x
Mapping Source Code Instructions to Hardware Scheduling Mapping Parallelism Models to FPGA Hardware Memory Types
Intel oneAPI FPGA Development x
FPGA Flow Terminology Intel oneAPI FPGA Development Flow Types of SYCL* FPGA Compilation FPGA Compilation Flags FPGA Workflows in IDEs
Types of SYCL* FPGA Compilation x
Separating Device and Host Code Compilation
Defining a Kernel for FPGAs x
Suggested Kernel Coding Styles Single Work-Item Kernels
Single Work-Item Kernels x
Single Work-item Kernel Design Guidelines Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
Strategies for Inferring the Accumulator
Debugging and Verifying Your Design x
Device Selectors for FPGA printf Command Restrictions Emulate and Debug Your Design Evaluate Your Kernel Through Simulation
Emulate and Debug Your Design x
Emulator Environment Variables Compile and Emulate Your Design Limitations of the Emulator Troubleshooting Discrepancies in Hardware and Emulator Results Emulator Known Issues
Evaluate Your Kernel Through Simulation x
Debug During Verification Simulation Prerequisites Installing the Questa*-Intel FPGA Edition Software Set Up the Simulation Environment Compile a Kernel for Simulation Simulate Your Kernel Viewing Simulation Waveforms Troubleshooting Simulator Issues
Analyzing Your Design x
Analyze the FPGA Early Image Analyze the FPGA Image Review the FPGA Optimization Report Quartus (Static) Summary Intel® FPGA Dynamic Profiler for DPC++ System-level Profiling Using the Intercept Layer for OpenCL™ Applications
Review the FPGA Optimization Report x
Loop Analysis Bottlenecks Viewer Area Estimates System Viewer Kernel Memory Viewer Schedule Viewer Access HLD FPGA Reports in JSON Format
Quartus (Static) Summary x
Timing Failures
Intel® FPGA Dynamic Profiler for DPC++ x
Measure Kernel Performance Instrument the Kernel Pipeline with Performance Counters (-Xsprofile) Obtain Profiling Data During Run Time Reduce Area Resource Use While Profiling Profiler Analyses of Example SYCL* Design Scenarios Limitations
Obtain Profiling Data During Run Time x
Invoke the Profiler Runtime Wrapper to Obtain Profiling Data Use Intel® VTune™ Profiler
Use Intel® VTune™ Profiler x
Interpret Performance Counter Data
System-level Profiling Using the Intercept Layer for OpenCL™ Applications x
Set Up the Intercept Layer for OpenCL™ Applications
Optimizing Your Host Application x
Throughput Resource Use Multi-Threaded Host Application Utilizing Hardware Kernel Invocation Queue Double Buffering Host Utilizing Kernel Invocation Queue N-Way Buffering to Overlap Kernel Execution Prepinning Memory Simple Host-Device Streaming Buffered Host-Device Streaming
Double Buffering Host Utilizing Kernel Invocation Queue x
Applying Double-Buffering Using the Intercept Layer for OpenCL™ Applications
Integrating Your RTL IP Core Into a System x
Synthesize Your RTL IP Core with Intel Quartus Prime Software Add RTL IP Component into a Platform Designer System Add an RTL IP Component into an Intel® Quartus® Prime Project Encrypt RTL IP Components for Distribution
RTL IP Core Kernel Interfaces x
Kernel Argument Interfaces Memory-Mapped (MM) Agent Kernel Invocation Interface Ready/Valid Handshaking Kernel Invocation Interface Memory-Mapped Host Interfaces
Memory-Mapped Host Interfaces x
Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the annotated_arg Class Memory-Mapped Host Interfaces Using Accessors (Deprecated) Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the mmhost Macro
Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the annotated_arg Class x
Buffer Locations in Memory-Mapped Host Interfaces The annotated_arg Template Class
Loops x
Refactor the Loop-Carried Data Dependency Relax Loop-Carried Dependency Transfer Loop-Carried Dependency to Local Memory Minimize the Memory Dependencies for Loop Pipelining Unroll Loops Fuse Loops to Reduce Overhead and Improve Performance Optimize Loops With Loop Speculation Remove Loop Bottlenecks Improve fMAX/II with Shannonization Optimize Inner Loop Throughput Improve Loop Performance by Caching Data in On-Chip Memory
Pipes x
Host Pipes Pipes Extension Emulate Applications with a Pipe That Reads or Writes to an I/O Pipe
Host Pipes x
Host Pipe Declaration Host Pipe API Host Pipes RTL Interfaces protocol_name::avalon_streaming_uses_ready protocol_name::avalon_streaming protocol_name::avalon_mm protocol_name::avalon_mm_uses_ready Avalon Steaming Sideband Signals
Pipes Extension x
Key Properties of a Pipe Accessing Pipes The pipe Class and its Use I/O Pipes Characteristics of Pipes Restrictions of Pipes Guidelines for Designing Pipes The atomic_fence Function and Pipes
Data Types and Arithmetic Operations x
Optimize Floating-point Operation Avoid Expensive Functions Variable-Precision Data Type Support
Variable-Precision Data Type Support x
Advantages and Limitations of Variable Precision Data Types Declare and Use the AC Data Types
Declare and Use the AC Data Types x
Declare the ac_int Data Type Declare the ac_fixed Data Type Declare the ac_complex Data Type Declare the ap_float Data Type
Declare the ap_float Data Type x
Conversion Rules for the ap_float Data Type Operations with Explicit Precision Controls Comparison Operators Additional ap_float Functions Additional Data Types Provided by the ap_float.hpp Header File Quality of Results and the ap_float Data Type
Parallelism x
Pipelined Kernels NDRange Kernels Asynchronous Parallelism Within Kernels (task_sequence)
Pipelined Kernels x
Stable Arguments
Asynchronous Parallelism Within Kernels (task_sequence) x
Task Functions task_sequence Use Cases
Memories and Memory Operations x
The device_global Extension (Beta) Memory Accesses Kernel Variable Accesses
Memory Accesses x
Load-Store Units Global Memory Accesses Optimization Perform Kernel Computations Using Local or Private Memory Local and Private Memory Accesses Optimization Annotating Unified Shared Memory Pointers Zero-Copy Memory Access Additional Recommendations
Load-Store Units x
Load-Store Unit Styles Load-Store Unit Modifiers Load-Store Unit Controls
Global Memory Accesses Optimization x
Global Memory Bandwidth Use Calculation Manual Partition of Global Memory Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) Partitioning Buffers Across Memory Channels of the Same Memory Type Ignoring Dependencies Between Accessor Arguments Contiguous Memory Accesses Static Memory Coalescing
Libraries x
Use SYCL Shared Library With Third-Party Applications Use of RTL Libraries for FPGA Object Manifest File Syntax of an RTL Library Restrictions and Limitations in RTL Support Intel® Stratix® 10 and Intel Agilex® 7 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Libraries Stall-Free RTL
Additional FPGA Acceleration Flow Considerations x
FPGA-CPU Interaction FPGA BSPs and Boards Targeting Multiple Homogeneous FPGA Devices Targeting Multiple Platforms Split Kernel into Multiple FPGA Images (Linux only)
FPGA BSPs and Boards x
FPGA Board Initialization Obtain FPGA Hardware Image Information Extracting the FPGA Hardware Configuration (.aocx) File from a Multiarchitecture Binary File
Additional SYCL* HLS Flow Considerations x
IP Component Reset Behavior
FPGA Optimization Flags, Attributes, Pragmas, and Extensions x
Optimization Flags Optimization Targets Kernel Variables Kernel Attributes Memory Attributes Loop Directives Floating-Point Pragmas Latency Controls (Beta)
Optimization Flags x
Specify Schedule FMAX Target for Kernels (-Xsclock=<clock target>) Create a 2xclock Interface (-Xsuse-2xclock) Disable Burst-Interleaving of Global Memory (-Xsno-interleaving=<global_memory_name>) Force Ring Interconnect for Global Memory (-Xsglobal-ring) Force a Single Store Ring to Reduce Area (-Xsforce-single-store-ring) Force Fewer Read Data Reorder Units to Reduce Area (-Xsnum-reorder) Disable Hardware Kernel Invocation Queue (-Xsno-hardware-kernel-invocation-queue) Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking) Disable Automatic Fusion of Loops (-Xsdisable-auto-loop-fusion) Fuse Adjacent Loops With Unequal Trip Counts (-Xsenable-unequal-tc-fusion) Pipeline Loops in Non-task Kernels (-Xsauto-pipeline) Control Semantics of Floating-Point Operations (-fp-model=<value>) Modify the Rounding Mode of Floating-point Operations (-Xsrounding=<rounding_type>) Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>) Enable the Read-Only Cache for Read-Only Accessors (-Xsread-only-cache-size=<N>) Control Hardware Implementation of the Supported Data Types and Math Operations (-Xsdsp-mode=<option>) Generate Register Map Wrapper (-Xsregister-map-wrapper-type)
Optimization Targets x
Minimum Latency Flow Balanced Throughput-Area Trade-Offs Flow
Kernel Attributes x
Specify Schedule FMAX Target for Kernels Specify a Workgroup Size Specify Number of SIMD Work Items Omit Hardware that Generates and Dispatches Kernel IDs Omit Hardware to Support the no_global_work_offset Attribute in parallel_for Kernels Reduce Kernel Area and Latency
Loop Directives x
disable_loop_pipelining Attribute initiation_interval Attribute ivdep Attribute loop_coalesce Attribute max_concurrency Attribute max_interleaving Attribute speculated_iterations Attribute unroll Pragma Loop Fuse Functions and nofusion Attribute max_reinvocation_delay Attribute (Beta)
Quick Reference x
Algorithmic C Data Types Floating Point Pragmas FPGA Accessor Properties FPGA Extensions FPGA Kernel Attributes FPGA Local Memory Function Latency Control Properties (Beta) FPGA LSU Controls FPGA Loop Directives FPGA Memory Attributes FPGA Optimization Flags Pipe API
Intel® oneAPI FPGA Handbook
Introduction To FPGA Design Concepts
Intel oneAPI FPGA Development
Defining a Kernel for FPGAs
Debugging and Verifying Your Design
Analyzing Your Design
Optimizing Your Kernel
Optimizing Your Host Application
Integrating Your RTL IP Core Into a System
RTL IP Core Kernel Interfaces
Loops
Pipes
Data Types and Arithmetic Operations
Parallelism
Memories and Memory Operations
Libraries
Additional FPGA Acceleration Flow Considerations
Additional SYCL* HLS Flow Considerations
FPGA Optimization Flags, Attributes, Pragmas, and Extensions
Quick Reference
Additional Information
Document Revision History for the Intel oneAPI FPGA Handbook
Notices and Disclaimers

Host Pipes RTL Interfaces

This section provides a summary of interfacing with host pipes in your IP based on the choice of protocol.

Host pipes support Avalon® streaming and memory-mapped interfaces. Refer to the Intel® Avalon Interface Specifications for details about these protocols.

For Avalon® memory-mapped protocols, register addresses in the CRA are specified in the generated kernel header file in the project directory. Refer to Register Map Header File for further details on CRA agent registers.

protocol_name::avalon_streaming_uses_ready

This is the default protocol.

This protocol allows the sink to backpressure by deasserting the ready signal. The sink signifies that it is ready to consume data by asserting the ready signal. On the cycle where the sink asserts the ready signal, the source must wait for the ready_latency signal to cycle before responding with valid and data signals, where the property specifies the ready_latency in the host pipe declaration.

Host-to-Device Pipe

When the uses_valid property is set to false and the ready signal is asserted by the kernel and sampled by the host, the host must wait ready_latency cycles before the value on the data interface is sampled by the kernel and consumed.

When the uses_valid property is set to true and the ready signal is asserted by the kernel and sampled by the host, the host must wait ready_latency cycles before inserting the valid signal. The data interface is not sampled or consumed by the kernel until the valid signal is asserted.

Device-to-Host Pipe

When the uses_valid property is set to true and the host asserts the ready signal, the kernel replies with valid=1 and qualified data (if available) ready_latency cycles after the corresponding ready was first asserted.

When the uses_valid property is set to false and the host asserts the ready signal, the kernel replies with qualified data ready_latency cycles after the corresponding ready was first asserted.

protocol_name::avalon_streaming

With this choice of protocol, the ready signal is not exposed by the host pipe, and the sink cannot backpressure.

The valid signal qualifies data transfer from source to sink per cycle when the uses_valid property is set to true. When the uses_valid property is set to false, the source implicitly provides a valid output on every cycle, and the sink assumes a valid input on every cycle.

Host-to-Device Pipe

When the uses_valid property is set to false, the kernel samples and processes the value on the host pipe data interfaces on each cycle.

When the uses_valid property is set to true, the kernel samples and processes the value on the host pipe data interface on each cycle that the valid signal is asserted.

Device-to-Host Pipe

When the uses_valid property is set to false, the host must sample and process values on the host pipe data interface every clock cycle. Failure to do so causes the data to be dropped.

When the uses_valid property is set to true, the host must sample and process values on the host pipe data interface every clock cycle that the valid signal is asserted. Failure to do so causes the data to be dropped.

protocol_name::avalon_mm

With this protocol, an implicit ready signal is held high, and the sink cannot backpressure.

The uses_valid property must also be set to true. Both the valid and data signals for the pipe are stored in registers implemented in the CRA agent.

Device-to-Host Pipe

Because the sink (host) cannot backpressure, data must be immediately consumed when it is available or it might be lost.

For an RTL IP component kernel, the surrounding system should be carefully architected to ensure that read timing is in sync with write timing for the IP without handshaking. Simulating such designs in the HLS flow might result in undefined behavior because the generated testbench might not be able to guarantee this timing.

Host-to-Device Pipe

The host writes a 1 to the valid register to indicate that the value in the data register is qualified. When the kernel has consumed this data, the kernel automatically clears the value in the valid register. A cleared valid register signifies that the host is free to write a new value into the data register.

protocol_name::avalon_mm_uses_ready

With this protocol, an additional register in the CRA is created to hold the ready signal. You must set the uses_valid property to true.

Host-to-Device Pipe

The kernel writes a 1 to the ready register when it is available to receive data. The host writes a 1 to the valid register to indicate that the value in the data register is qualified.

Device-to-Host Pipe

The kernel writes a 1 to the valid register to indicate that the value in the data register is qualified. This value is held in the data register until the host writes a 1 to the ready register, which signifies that the host has consumed valid data from the data register. The kernel clears the ready register when the kernel has written subsequent qualified data and the valid register.

Avalon Steaming Sideband Signals

IMPORTANT:
Support for Avalon streaming interface sideband signals has beta-level support. The implementation of sideband signal support might change in a future release.

Enable Avalon streaming sideband signal support by using the StreamingBeat struct provided by the pipes_ext.hpp header file. The StreamingBeat struct generates sideband signals only when used with a host pipe. Other types of pipes do not support sideband signals.

To use the StreamingBeatstruct, include the pipes_ext.hpp header file:

$INTELFPGAOCLSDKROOT/include/sycl/ext/intel/prototype/pipes_ext.hpp

Using the StreamingBeat struct with the uses_packets property set to true adds two additional 1-bit signals to the Avalon interface, start_of_packet (sop), and end_of_packet (eop).

Assert the sop signal when you send the first beat of the packet along with a valid signal assertion. Assert the eop signal when you send the last beat, along with a valid signal assertion. You can assert sop and eop signals in the same cycle for a single packet transfer transaction. The sop signal can also be asserted on the cycle immediately after the eop signal was asserted for the previous packet.

The third property for the StreamingBeatstruct signifies use_empty. When use_empty is set to true, it adds an empty signal that is bits long. The empty signal indicates the number of symbols that are empty during the eop cycle.

Empty symbols are always the last symbols in the data. That is, the symbols carried by low-order bits when first_symbol_in_high_order_bits is true, or the high-order bits if first_symbol_in_high_order_bits is set to false.

You must set use_empty for all packet interfaces that carry more than one symbol of data that have a variable length packet format.

The following example uses the StreamingBeatstruct with the uses_packets and use_empty properties both set to true. The size of the PipeData type is forced to a multiple of the kBitsPerSymbol value, which is passed to the associated host pipe declaration.

using PipeData = ac_int<kBitsPerSymbol * kSymbolsPerBeat, false>;
using StreamingBeatData = sycl::ext::intel::experimental::StreamingBeat<PipeData, true, true>;

When you define the host pipe, set the data type to the StreamingBeatData struct:

using H2DPipe = sycl::ext::intel::experimental::pipe<H2DPipeID, StreamingBeatData>;

The following code example instantiates a StreamingBeat struct and writes to the pipe (from the host):

bool sop = true;
bool eop = false;
int empty = 0;
PipeData data = ...
StreamingBeatData in_beat(data, sop, eop, empty);
H2DPipe::write(q, in_beat);

The following code example reads from the pipe and extracts the sideband signals (from device):

StreamingBeat in_beat = H2DPipe::read();
PipeData in_data = in_beat.data;
bool sop = in_beat.sop;
bool eop = in_beat.eop;
int empty = in_beat.empty;
Parent topic: Host Pipes
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