Visible to Intel only — GUID: GUID-B6BC2725-7ECF-411B-99F9-252B2BAE5F76
Visible to Intel only — GUID: GUID-B6BC2725-7ECF-411B-99F9-252B2BAE5F76
FPGA Flow Terminology
Field-programmable gate arrays (FPGAs) are configurable integrated circuits that you can program to implement arbitrary circuit topologies. Classified as spatial compute architectures, FPGAs differ significantly from fixed Instruction Set Architecture (ISA) devices such as CPUs and GPUs. FPGAs offer a different set of optimization trade-offs from these traditional accelerator devices.
While you can compile SYCL* code for CPU, GPU or FPGA, the compiling process for FPGA development is somewhat different than that for CPU or GPU development.
The following table summarizes terminologies used in describing the FPGA flow:
Term |
Definition |
---|---|
Device code |
SYCL source code that executes on a SYCL device rather than the host. Device code is specified via lambda expression, functor, or kernel class. |
Host code |
SYCL source code that is compiled by the host compiler and executes on the host rather than the device. In the SYCL HLS flow, your host code becomes the testbench for your IP component. |
FPGA emulator image |
The device image resulting from compiling for the FPGA emulator. See FPGA Emulator. |
FPGA Optimization Report |
The device image resulting from the FPGA Optimization Report compilation stage. See FPGA Optimization Report. Compiling for the FPGA Optimization Report also provides an RTL IP core version of your kernel (device code) that you can integrate into a larger FPGA hardware design. |
FPGA hardware image |
The device image resulting from the hardware image compilation stage. See FPGA Optimization Report and FPGA Hardware. Compiling for the FPGA hardware image also provides an RTL IP core version of your kernel (device code) that you can integrate into a larger FPGA hardware design. |