Developer Guide

Intel oneAPI FPGA Handbook

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Date 2/07/2024
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Document Table of Contents
Document Table of Contents x
Intel® oneAPI FPGA Handbook Introduction To FPGA Design Concepts Intel oneAPI FPGA Development Defining a Kernel for FPGAs Debugging and Verifying Your Design Analyzing Your Design Optimizing Your Kernel Optimizing Your Host Application Integrating Your RTL IP Core Into a System RTL IP Core Kernel Interfaces Loops Pipes Data Types and Arithmetic Operations Parallelism Memories and Memory Operations Libraries Additional FPGA Acceleration Flow Considerations Additional SYCL* HLS Flow Considerations FPGA Optimization Flags, Attributes, Pragmas, and Extensions Quick Reference Additional Information Document Revision History for the Intel oneAPI FPGA Handbook Notices and Disclaimers
Introduction To FPGA Design Concepts x
FPGA Architecture Overview Concepts of FPGA Hardware Design How Source Code Becomes a Custom Hardware Datapath
How Source Code Becomes a Custom Hardware Datapath x
Mapping Source Code Instructions to Hardware Scheduling Mapping Parallelism Models to FPGA Hardware Memory Types
Intel oneAPI FPGA Development x
FPGA Flow Terminology Intel oneAPI FPGA Development Flow Types of SYCL* FPGA Compilation FPGA Compilation Flags FPGA Workflows in IDEs
Types of SYCL* FPGA Compilation x
Separating Device and Host Code Compilation
Defining a Kernel for FPGAs x
Suggested Kernel Coding Styles Single Work-Item Kernels
Single Work-Item Kernels x
Single Work-item Kernel Design Guidelines Avoid Pointer Aliasing Construct "Well-Formed" Loops Minimize Loop-Carried Dependencies Avoid Complex Loop Exit Conditions Convert Nested Loops into a Single Loop Avoid Conditional Loops Declare Variables in the Deepest Scope Possible Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
Strategies for Inferring the Accumulator
Debugging and Verifying Your Design x
Device Selectors for FPGA printf Command Restrictions Emulate and Debug Your Design Evaluate Your Kernel Through Simulation
Emulate and Debug Your Design x
Emulator Environment Variables Compile and Emulate Your Design Limitations of the Emulator Troubleshooting Discrepancies in Hardware and Emulator Results Emulator Known Issues
Evaluate Your Kernel Through Simulation x
Debug During Verification Simulation Prerequisites Installing the Questa*-Intel FPGA Edition Software Set Up the Simulation Environment Compile a Kernel for Simulation Simulate Your Kernel Viewing Simulation Waveforms Troubleshooting Simulator Issues
Analyzing Your Design x
Analyze the FPGA Early Image Analyze the FPGA Image Review the FPGA Optimization Report Quartus (Static) Summary Intel® FPGA Dynamic Profiler for DPC++ System-level Profiling Using the Intercept Layer for OpenCL™ Applications
Review the FPGA Optimization Report x
Loop Analysis Bottlenecks Viewer Area Estimates System Viewer Kernel Memory Viewer Schedule Viewer Access HLD FPGA Reports in JSON Format
Quartus (Static) Summary x
Timing Failures
Intel® FPGA Dynamic Profiler for DPC++ x
Measure Kernel Performance Instrument the Kernel Pipeline with Performance Counters (-Xsprofile) Obtain Profiling Data During Run Time Reduce Area Resource Use While Profiling Profiler Analyses of Example SYCL* Design Scenarios Limitations
Obtain Profiling Data During Run Time x
Invoke the Profiler Runtime Wrapper to Obtain Profiling Data Use Intel® VTune™ Profiler
Use Intel® VTune™ Profiler x
Interpret Performance Counter Data
System-level Profiling Using the Intercept Layer for OpenCL™ Applications x
Set Up the Intercept Layer for OpenCL™ Applications
Optimizing Your Host Application x
Throughput Resource Use Multi-Threaded Host Application Utilizing Hardware Kernel Invocation Queue Double Buffering Host Utilizing Kernel Invocation Queue N-Way Buffering to Overlap Kernel Execution Prepinning Memory Simple Host-Device Streaming Buffered Host-Device Streaming
Double Buffering Host Utilizing Kernel Invocation Queue x
Applying Double-Buffering Using the Intercept Layer for OpenCL™ Applications
Integrating Your RTL IP Core Into a System x
Synthesize Your RTL IP Core with Intel Quartus Prime Software Add RTL IP Component into a Platform Designer System Add an RTL IP Component into an Intel® Quartus® Prime Project Encrypt RTL IP Components for Distribution
RTL IP Core Kernel Interfaces x
Kernel Argument Interfaces Memory-Mapped (MM) Agent Kernel Invocation Interface Ready/Valid Handshaking Kernel Invocation Interface Memory-Mapped Host Interfaces
Memory-Mapped Host Interfaces x
Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the annotated_arg Class Memory-Mapped Host Interfaces Using Accessors (Deprecated) Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the mmhost Macro
Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the annotated_arg Class x
Buffer Locations in Memory-Mapped Host Interfaces The annotated_arg Template Class
Loops x
Refactor the Loop-Carried Data Dependency Relax Loop-Carried Dependency Transfer Loop-Carried Dependency to Local Memory Minimize the Memory Dependencies for Loop Pipelining Unroll Loops Fuse Loops to Reduce Overhead and Improve Performance Optimize Loops With Loop Speculation Remove Loop Bottlenecks Improve fMAX/II with Shannonization Optimize Inner Loop Throughput Improve Loop Performance by Caching Data in On-Chip Memory
Pipes x
Host Pipes Pipes Extension Emulate Applications with a Pipe That Reads or Writes to an I/O Pipe
Host Pipes x
Host Pipe Declaration Host Pipe API Host Pipes RTL Interfaces
Pipes Extension x
Key Properties of a Pipe Accessing Pipes The pipe Class and its Use I/O Pipes Characteristics of Pipes Restrictions of Pipes Guidelines for Designing Pipes The atomic_fence Function and Pipes
Data Types and Arithmetic Operations x
Optimize Floating-point Operation Avoid Expensive Functions Variable-Precision Data Type Support
Variable-Precision Data Type Support x
Advantages and Limitations of Variable Precision Data Types Declare and Use the AC Data Types
Declare and Use the AC Data Types x
Declare the ac_int Data Type Declare the ac_fixed Data Type Declare the ac_complex Data Type Declare the ap_float Data Type
Declare the ap_float Data Type x
Conversion Rules for the ap_float Data Type Operations with Explicit Precision Controls Comparison Operators Additional ap_float Functions Additional Data Types Provided by the ap_float.hpp Header File Quality of Results and the ap_float Data Type
Parallelism x
Pipelined Kernels NDRange Kernels Asynchronous Parallelism Within Kernels (task_sequence)
Pipelined Kernels x
Stable Arguments
Asynchronous Parallelism Within Kernels (task_sequence) x
Task Functions task_sequence Use Cases
Memories and Memory Operations x
The device_global Extension (Beta) Memory Accesses Kernel Variable Accesses
Memory Accesses x
Load-Store Units Global Memory Accesses Optimization Perform Kernel Computations Using Local or Private Memory Local and Private Memory Accesses Optimization Annotating Unified Shared Memory Pointers Zero-Copy Memory Access Additional Recommendations
Load-Store Units x
Load-Store Unit Styles Load-Store Unit Modifiers Load-Store Unit Controls
Global Memory Accesses Optimization x
Global Memory Bandwidth Use Calculation Manual Partition of Global Memory Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) Partitioning Buffers Across Memory Channels of the Same Memory Type Ignoring Dependencies Between Accessor Arguments Contiguous Memory Accesses Static Memory Coalescing
Libraries x
Use SYCL Shared Library With Third-Party Applications Use of RTL Libraries for FPGA Object Manifest File Syntax of an RTL Library Restrictions and Limitations in RTL Support Intel® Stratix® 10 and Intel Agilex® 7 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Libraries Stall-Free RTL
Additional FPGA Acceleration Flow Considerations x
FPGA-CPU Interaction FPGA BSPs and Boards Targeting Multiple Homogeneous FPGA Devices Targeting Multiple Platforms Split Kernel into Multiple FPGA Images (Linux only)
FPGA BSPs and Boards x
FPGA Board Initialization Obtain FPGA Hardware Image Information Extracting the FPGA Hardware Configuration (.aocx) File from a Multiarchitecture Binary File
Additional SYCL* HLS Flow Considerations x
IP Component Reset Behavior
FPGA Optimization Flags, Attributes, Pragmas, and Extensions x
Optimization Flags Optimization Targets Kernel Variables Kernel Attributes Memory Attributes Loop Directives Floating-Point Pragmas Latency Controls (Beta)
Optimization Flags x
Specify Schedule FMAX Target for Kernels (-Xsclock=<clock target>) Create a 2xclock Interface (-Xsuse-2xclock) Disable Burst-Interleaving of Global Memory (-Xsno-interleaving=<global_memory_name>) Force Ring Interconnect for Global Memory (-Xsglobal-ring) Force a Single Store Ring to Reduce Area (-Xsforce-single-store-ring) Force Fewer Read Data Reorder Units to Reduce Area (-Xsnum-reorder) Disable Hardware Kernel Invocation Queue (-Xsno-hardware-kernel-invocation-queue) Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking) Disable Automatic Fusion of Loops (-Xsdisable-auto-loop-fusion) Fuse Adjacent Loops With Unequal Trip Counts (-Xsenable-unequal-tc-fusion) Pipeline Loops in Non-task Kernels (-Xsauto-pipeline) Control Semantics of Floating-Point Operations (-fp-model=<value>) Modify the Rounding Mode of Floating-point Operations (-Xsrounding=<rounding_type>) Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>) Enable the Read-Only Cache for Read-Only Accessors (-Xsread-only-cache-size=<N>) Control Hardware Implementation of the Supported Data Types and Math Operations (-Xsdsp-mode=<option>) Generate Register Map Wrapper (-Xsregister-map-wrapper-type)
Optimization Targets x
Minimum Latency Flow Balanced Throughput-Area Trade-Offs Flow
Kernel Attributes x
Specify Schedule FMAX Target for Kernels Specify a Workgroup Size Specify Number of SIMD Work Items Omit Hardware that Generates and Dispatches Kernel IDs Omit Hardware to Support the no_global_work_offset Attribute in parallel_for Kernels Reduce Kernel Area and Latency
Loop Directives x
disable_loop_pipelining Attribute initiation_interval Attribute ivdep Attribute loop_coalesce Attribute max_concurrency Attribute max_interleaving Attribute speculated_iterations Attribute unroll Pragma Loop Fuse Functions and nofusion Attribute max_reinvocation_delay Attribute (Beta)
Quick Reference x
Algorithmic C Data Types Floating Point Pragmas FPGA Accessor Properties FPGA Extensions FPGA Kernel Attributes FPGA Local Memory Function Latency Control Properties (Beta) FPGA LSU Controls FPGA Loop Directives FPGA Memory Attributes FPGA Optimization Flags Pipe API
Intel® oneAPI FPGA Handbook
Introduction To FPGA Design Concepts
Intel oneAPI FPGA Development
Defining a Kernel for FPGAs
Debugging and Verifying Your Design
Analyzing Your Design
Optimizing Your Kernel
Optimizing Your Host Application
Integrating Your RTL IP Core Into a System
RTL IP Core Kernel Interfaces
Loops
Pipes
Data Types and Arithmetic Operations
Parallelism
Memories and Memory Operations
Libraries
Additional FPGA Acceleration Flow Considerations
Additional SYCL* HLS Flow Considerations
FPGA Optimization Flags, Attributes, Pragmas, and Extensions
Quick Reference
Additional Information
Document Revision History for the Intel oneAPI FPGA Handbook
Notices and Disclaimers

Single Work-item Kernel Design Guidelines

If your kernels contain loop structures, follow the Intel®-recommended guidelines to construct the kernels in a way that allows the Intel® oneAPI DPC++/C++ Compiler to analyze them effectively. Well-structured loops are particularly important to aid the compiler in generating a pipeline parallel datapath for loops.

Avoid Pointer Aliasing

If your kernels have pointer arguments, you can improve the throughput of the design if the Intel® oneAPI DPC++/C++ Compiler can prove those arguments never point to the same memory location. It is possible to provide the compiler with information about pointer arguments in kernels. For more information, refer to Ignoring Dependencies Between Accessor Arguments.

Construct "Well-Formed" Loops

A well-formed loop has an exit condition that compares against an integer bound and has a simple induction increment. Including well-formed loops in your kernel improves performance because the Intel® oneAPI DPC++/C++ Compiler can analyze these loops efficiently.

The following example is a well-formed loop: 

for (i = 0; i < N; i++) {
  //statements
}
NOTE:

Well-formed nested loops also contribute to maximizing kernel performance.

The following example is a well-formed nested loop structure: 

for (i = 0; i < N; i++) {
  //statements
  for(j = 0; j < M; j++) {
    //statements
  }
}

Minimize Loop-Carried Dependencies

The following loop structure creates a loop-carried dependence because each loop iteration reads data written by the previous iteration: 

for (int i = 0; i < N; i++) {
  A[i] = A[i - 1] + i;
}

As a result, each read operation cannot proceed until the write operation from the previous iteration completes. The presence of loop-carried dependencies decreases the extent of pipeline parallelism that the Intel® oneAPI DPC++/C++ Compiler can achieve, which reduces kernel performance.

The Intel® oneAPI DPC++/C++ Compiler performs a static memory dependence analysis on loops to determine the extent of parallelism that it can achieve. In some cases, the Intel® oneAPI DPC++/C++ Compiler might assume loop-carried dependence:

  • Between two array accesses and as a result, extract less pipeline parallelism.
  • If it cannot resolve the dependencies at compilation time because of unknown variables or complex indexing expressions.

To minimize loop-carried dependencies, follow these guidelines whenever possible:

  • Avoid pointer arithmetic. Compiler output is suboptimal when the kernel accesses arrays by dereferencing pointer values derived from arithmetic operations. For example, avoid accessing an array in the following manner: 
    for (int i = 0; i < N; i++) {
  int t = *(A++);
  *A = t;
}
  • Introduce simple, affine array indexes. Avoid the following types of complex array indexes because the Intel® oneAPI DPC++/C++ Compiler cannot analyze them effectively, which might lead to suboptimal compiler output:
    • Non-constants in array indexes. For example, A[K + i], where i is the loop index variable and K is an unknown variable.
    • Multiple index variables in the same subscript location. For example, A[i + 2 × j], where i and j are loop index variables for a double nested loop.
NOTE:

The Intel® oneAPI DPC++/C++ Compiler can analyze the array index A[i][j] effectively because the index variables are in different subscripts.

Avoid Complex Loop Exit Conditions

The Intel® oneAPI DPC++/C++ Compiler evaluates exit conditions to determine if subsequent loop iterations can enter the loop pipeline. Occasionally, the Intel® oneAPI DPC++/C++ Compiler requires memory accesses or complex operations to evaluate the exit condition. In these cases, subsequent iterations cannot launch until the evaluation completes, decreasing the overall loop performance.

Convert Nested Loops into a Single Loop

To maximize performance, combine nested loops into a single form whenever possible. Restructuring nested loops into a single loop reduces hardware footprint and computational overhead between loop iterations.

The following code examples illustrate the conversion of a nested loop into a single loop:

Conversion of a Nested Loop into a Single Loop

Nested Loop

Converted Single Loop 

for (i = 0; i < N; i++) {
  //statements
  for (j = 0; j < M; j++) {
    //statements          
  }
  //statements
}
 
for (i = 0; i < N*M; i++) {
  //statements
}

Avoid Conditional Loops

To maximize performance, avoid declaring conditional loops. Conditional loops are tuples of loops that are declared within conditional statements such that one and only one of the loops is expected to be reached. These loops cannot be efficiently parallelized and result in a serialized implementation.

The following code examples illustrate the conversion of conditional loops to a more optimal implementation:

Conversion of a Conditional Loop to an Optimized Loop

Conditional Loops

Converted Loop 

if (condition) {
  for (int i = 0; i < m; i++) {
    // statements
  }
}
else {
  for (int i = 0; i < m; i++) {
    // statements
  }
}
 
for (int i = 0; i < m; i++) {
  if (condition) {
    // statements
  }
  else {
    // statements
  }
}

Declare Variables in the Deepest Scope Possible

To reduce hardware resources necessary for implementing a variable, declare the variable prior to its use in a loop. Declaring variables in the deepest scope possible minimizes data dependencies and hardware use because the Intel® oneAPI DPC++/C++ Compiler does not need to preserve the variable data across loops that do not use variables.

Consider the following example: 

int a[N];
for (int i = 0; i < m; ++i) {
  int b[N];
  for (int j = 0; j < n; ++j) {
    // statements
  }
}

The array a requires more resources to implement than the array b because array a is declared at a broader scope. To reduce hardware use, declare array a outside the inner loop unless it is necessary to maintain the data through iterations of the outer loop, as shown in the following: 


for (int i = 0; i < m; ++i) {
  int a[N];
  int b[N];
  for (int j = 0; j < n; ++j) {
    // statements
  }
}
TIP:

Overwriting all values of a variable in the deepest scope possible also reduces resources necessary to present the variable.

Parent topic: Single Work-Item Kernels
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