Developer Guide

Intel oneAPI FPGA Handbook

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Date 2/07/2024
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Document Table of Contents
Document Table of Contents x
Intel® oneAPI FPGA Handbook Introduction To FPGA Design Concepts Intel oneAPI FPGA Development Defining a Kernel for FPGAs Debugging and Verifying Your Design Analyzing Your Design Optimizing Your Kernel Optimizing Your Host Application Integrating Your RTL IP Core Into a System RTL IP Core Kernel Interfaces Loops Pipes Data Types and Arithmetic Operations Parallelism Memories and Memory Operations Libraries Additional FPGA Acceleration Flow Considerations Additional SYCL* HLS Flow Considerations FPGA Optimization Flags, Attributes, Pragmas, and Extensions Quick Reference Additional Information Document Revision History for the Intel oneAPI FPGA Handbook Notices and Disclaimers
Introduction To FPGA Design Concepts x
FPGA Architecture Overview Concepts of FPGA Hardware Design How Source Code Becomes a Custom Hardware Datapath
How Source Code Becomes a Custom Hardware Datapath x
Mapping Source Code Instructions to Hardware Scheduling Mapping Parallelism Models to FPGA Hardware Memory Types
Intel oneAPI FPGA Development x
FPGA Flow Terminology Intel oneAPI FPGA Development Flow Types of SYCL* FPGA Compilation FPGA Compilation Flags FPGA Workflows in IDEs
Types of SYCL* FPGA Compilation x
Separating Device and Host Code Compilation
Defining a Kernel for FPGAs x
Suggested Kernel Coding Styles Single Work-Item Kernels
Single Work-Item Kernels x
Single Work-item Kernel Design Guidelines Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
Strategies for Inferring the Accumulator
Debugging and Verifying Your Design x
Device Selectors for FPGA printf Command Restrictions Emulate and Debug Your Design Evaluate Your Kernel Through Simulation
Emulate and Debug Your Design x
Emulator Environment Variables Compile and Emulate Your Design Limitations of the Emulator Troubleshooting Discrepancies in Hardware and Emulator Results Emulator Known Issues
Evaluate Your Kernel Through Simulation x
Debug During Verification Simulation Prerequisites Installing the Questa*-Intel FPGA Edition Software Set Up the Simulation Environment Compile a Kernel for Simulation Simulate Your Kernel Viewing Simulation Waveforms Troubleshooting Simulator Issues
Analyzing Your Design x
Analyze the FPGA Early Image Analyze the FPGA Image Review the FPGA Optimization Report Quartus (Static) Summary Intel® FPGA Dynamic Profiler for DPC++ System-level Profiling Using the Intercept Layer for OpenCL™ Applications
Review the FPGA Optimization Report x
Loop Analysis Bottlenecks Viewer Area Estimates System Viewer Kernel Memory Viewer Schedule Viewer Access HLD FPGA Reports in JSON Format
Quartus (Static) Summary x
Timing Failures
Intel® FPGA Dynamic Profiler for DPC++ x
Measure Kernel Performance Instrument the Kernel Pipeline with Performance Counters (-Xsprofile) Obtain Profiling Data During Run Time Reduce Area Resource Use While Profiling Profiler Analyses of Example SYCL* Design Scenarios Limitations
Obtain Profiling Data During Run Time x
Invoke the Profiler Runtime Wrapper to Obtain Profiling Data Use Intel® VTune™ Profiler
Use Intel® VTune™ Profiler x
Interpret Performance Counter Data
System-level Profiling Using the Intercept Layer for OpenCL™ Applications x
Set Up the Intercept Layer for OpenCL™ Applications
Optimizing Your Host Application x
Throughput Resource Use Multi-Threaded Host Application Utilizing Hardware Kernel Invocation Queue Double Buffering Host Utilizing Kernel Invocation Queue N-Way Buffering to Overlap Kernel Execution Prepinning Memory Simple Host-Device Streaming Buffered Host-Device Streaming
Double Buffering Host Utilizing Kernel Invocation Queue x
Applying Double-Buffering Using the Intercept Layer for OpenCL™ Applications
Integrating Your RTL IP Core Into a System x
Synthesize Your RTL IP Core with Intel Quartus Prime Software Add RTL IP Component into a Platform Designer System Add an RTL IP Component into an Intel® Quartus® Prime Project Encrypt RTL IP Components for Distribution
RTL IP Core Kernel Interfaces x
Kernel Argument Interfaces Memory-Mapped (MM) Agent Kernel Invocation Interface Ready/Valid Handshaking Kernel Invocation Interface Memory-Mapped Host Interfaces
Memory-Mapped Host Interfaces x
Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the annotated_arg Class Memory-Mapped Host Interfaces Using Accessors (Deprecated) Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the mmhost Macro
Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the annotated_arg Class x
Buffer Locations in Memory-Mapped Host Interfaces The annotated_arg Template Class
Loops x
Refactor the Loop-Carried Data Dependency Relax Loop-Carried Dependency Transfer Loop-Carried Dependency to Local Memory Minimize the Memory Dependencies for Loop Pipelining Unroll Loops Fuse Loops to Reduce Overhead and Improve Performance Optimize Loops With Loop Speculation Remove Loop Bottlenecks Improve fMAX/II with Shannonization Optimize Inner Loop Throughput Improve Loop Performance by Caching Data in On-Chip Memory
Pipes x
Host Pipes Pipes Extension Emulate Applications with a Pipe That Reads or Writes to an I/O Pipe
Host Pipes x
Host Pipe Declaration Host Pipe API Host Pipes RTL Interfaces
Pipes Extension x
Key Properties of a Pipe Accessing Pipes The pipe Class and its Use I/O Pipes Characteristics of Pipes Restrictions of Pipes Guidelines for Designing Pipes The atomic_fence Function and Pipes
Data Types and Arithmetic Operations x
Optimize Floating-point Operation Avoid Expensive Functions Variable-Precision Data Type Support
Variable-Precision Data Type Support x
Advantages and Limitations of Variable Precision Data Types Declare and Use the AC Data Types
Declare and Use the AC Data Types x
Declare the ac_int Data Type Declare the ac_fixed Data Type Declare the ac_complex Data Type Declare the ap_float Data Type
Declare the ap_float Data Type x
Conversion Rules for the ap_float Data Type Operations with Explicit Precision Controls Comparison Operators Additional ap_float Functions Additional Data Types Provided by the ap_float.hpp Header File Quality of Results and the ap_float Data Type
Parallelism x
Pipelined Kernels NDRange Kernels Asynchronous Parallelism Within Kernels (task_sequence)
Pipelined Kernels x
Stable Arguments
Asynchronous Parallelism Within Kernels (task_sequence) x
Task Functions task_sequence Use Cases
Memories and Memory Operations x
The device_global Extension (Beta) Memory Accesses Kernel Variable Accesses
Memory Accesses x
Load-Store Units Global Memory Accesses Optimization Perform Kernel Computations Using Local or Private Memory Local and Private Memory Accesses Optimization Annotating Unified Shared Memory Pointers Zero-Copy Memory Access Additional Recommendations
Load-Store Units x
Load-Store Unit Styles Load-Store Unit Modifiers Load-Store Unit Controls Burst-Coalesce Static Coalescing Prefetch Cache Pipeline
Global Memory Accesses Optimization x
Global Memory Bandwidth Use Calculation Manual Partition of Global Memory Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) Partitioning Buffers Across Memory Channels of the Same Memory Type Ignoring Dependencies Between Accessor Arguments Contiguous Memory Accesses Static Memory Coalescing
Libraries x
Use SYCL Shared Library With Third-Party Applications Use of RTL Libraries for FPGA Object Manifest File Syntax of an RTL Library Restrictions and Limitations in RTL Support Intel® Stratix® 10 and Intel Agilex® 7 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Libraries Stall-Free RTL
Additional FPGA Acceleration Flow Considerations x
FPGA-CPU Interaction FPGA BSPs and Boards Targeting Multiple Homogeneous FPGA Devices Targeting Multiple Platforms Split Kernel into Multiple FPGA Images (Linux only)
FPGA BSPs and Boards x
FPGA Board Initialization Obtain FPGA Hardware Image Information Extracting the FPGA Hardware Configuration (.aocx) File from a Multiarchitecture Binary File
Additional SYCL* HLS Flow Considerations x
IP Component Reset Behavior
FPGA Optimization Flags, Attributes, Pragmas, and Extensions x
Optimization Flags Optimization Targets Kernel Variables Kernel Attributes Memory Attributes Loop Directives Floating-Point Pragmas Latency Controls (Beta)
Optimization Flags x
Specify Schedule FMAX Target for Kernels (-Xsclock=<clock target>) Create a 2xclock Interface (-Xsuse-2xclock) Disable Burst-Interleaving of Global Memory (-Xsno-interleaving=<global_memory_name>) Force Ring Interconnect for Global Memory (-Xsglobal-ring) Force a Single Store Ring to Reduce Area (-Xsforce-single-store-ring) Force Fewer Read Data Reorder Units to Reduce Area (-Xsnum-reorder) Disable Hardware Kernel Invocation Queue (-Xsno-hardware-kernel-invocation-queue) Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking) Disable Automatic Fusion of Loops (-Xsdisable-auto-loop-fusion) Fuse Adjacent Loops With Unequal Trip Counts (-Xsenable-unequal-tc-fusion) Pipeline Loops in Non-task Kernels (-Xsauto-pipeline) Control Semantics of Floating-Point Operations (-fp-model=<value>) Modify the Rounding Mode of Floating-point Operations (-Xsrounding=<rounding_type>) Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>) Enable the Read-Only Cache for Read-Only Accessors (-Xsread-only-cache-size=<N>) Control Hardware Implementation of the Supported Data Types and Math Operations (-Xsdsp-mode=<option>) Generate Register Map Wrapper (-Xsregister-map-wrapper-type)
Optimization Targets x
Minimum Latency Flow Balanced Throughput-Area Trade-Offs Flow
Kernel Attributes x
Specify Schedule FMAX Target for Kernels Specify a Workgroup Size Specify Number of SIMD Work Items Omit Hardware that Generates and Dispatches Kernel IDs Omit Hardware to Support the no_global_work_offset Attribute in parallel_for Kernels Reduce Kernel Area and Latency
Loop Directives x
disable_loop_pipelining Attribute initiation_interval Attribute ivdep Attribute loop_coalesce Attribute max_concurrency Attribute max_interleaving Attribute speculated_iterations Attribute unroll Pragma Loop Fuse Functions and nofusion Attribute max_reinvocation_delay Attribute (Beta)
Quick Reference x
Algorithmic C Data Types Floating Point Pragmas FPGA Accessor Properties FPGA Extensions FPGA Kernel Attributes FPGA Local Memory Function Latency Control Properties (Beta) FPGA LSU Controls FPGA Loop Directives FPGA Memory Attributes FPGA Optimization Flags Pipe API
Intel® oneAPI FPGA Handbook
Introduction To FPGA Design Concepts
Intel oneAPI FPGA Development
Defining a Kernel for FPGAs
Debugging and Verifying Your Design
Analyzing Your Design
Optimizing Your Kernel
Optimizing Your Host Application
Integrating Your RTL IP Core Into a System
RTL IP Core Kernel Interfaces
Loops
Pipes
Data Types and Arithmetic Operations
Parallelism
Memories and Memory Operations
Libraries
Additional FPGA Acceleration Flow Considerations
Additional SYCL* HLS Flow Considerations
FPGA Optimization Flags, Attributes, Pragmas, and Extensions
Quick Reference
Additional Information
Document Revision History for the Intel oneAPI FPGA Handbook
Notices and Disclaimers

Load-Store Unit Controls

The Intel® oneAPI DPC++/C++ Compiler allows you to control the LSU that is generated for global memory accesses via a set of templated options in the ext::intel::lsu class. The ext::intel::lsu class has two member functions, load() and store(), which allow loading from and storing to a global pointer, respectively. See also Annotating Unified Shared Memory Pointers.

NOTE:
Not all LSU control options listed below work with both load() and store() member functions. Not all styles and types are supported on every target device. Thus, the use of LSU control options results in a specific type of LSU.

LSU Control Options Available in the ext::intel::lsu Class
Control Syntax Value Default Value Supported Functionality
Burst-Coalesce ext::intel::burst_coalesce<B> B is a boolean False Load and store
Static Coalescing ext::intel::statically_coalesce<B> B is a boolean True Load and store
Prefetch ext::intel::prefetch<B> B is a boolean false Only loads
Cache ext::intel::cache<N> N is an integer greater than or equal to 0. 0 Only loads
Pipeline No option provided - Defaults above result in this. Load and store

Burst-Coalesce

Currently, not every combination of LSU controls is supported by the compiler. The following rules apply:

  • For store, the ext::intel::cache control must be 0 and the ext::intel::prefetch control must be false.
  • For load, if the ext::intel::cache control is set to a value greater than 0, then the ext::intel::burst_coalesce control must be set to true.
  • For load, exactly one of ext::intel::prefetch and ext::intel::burst_coalesce control options are allowed to be true.
  • For load, exactly one of ext::intel::prefetch and ext::intel::cache control options are allowed to be true.

The burst-coalesce control helps the Intel® oneAPI DPC++/C++ Compiler infer a burst-coalesced LSU. It can be combined with other attributes such as cache. For more details about this LSU type, refer to Burst-Coalesced Load-Store Units.

The following is an example of burst-coalesce LSU control: 

using BurstCoalescedLSU =
  ext::intel::lsu<ext::intel::burst_coalesce<true>,
                  ext::intel::statically_coalesce<false>>;
BurstCoalescedLSU::store(output_ptr, X);

Static Coalescing

The static-coalescing control helps the Intel® oneAPI DPC++/C++ Compiler turn on or off static coalescing for global memory accesses. Static coalescing of memory accesses is the default behavior of the compiler, so this feature can be used to turn off static coalescing. It can be combined with other attributes such as burst_coalesce. For more details about this memory optimization modifier, refer to Static Memory Coalescing.

The following is an example that shows how to use the LSU control to turn off static-coalescing LSU control: 

using NonStaticCoalescedLSU =
  ext::intel::lsu<ext::intel::burst_coalesce<true>, 
                  ext::intel::statically_coalesce<false>>;

int X = NonStaticCoalescedLSU::load(input_ptr);

Prefetch

The prefetch control helps the Intel® oneAPI DPC++/C++ Compiler infer a prefetch style LSU. The compiler honors this control only if it is physically possible. If there is a risk that an LSU is not functionally correct, it is not inferred. This control also works only for load accesses. For more details about this LSU type, refer to Prefetching Load-Store Units.

The following is an example of prefetch LSU control: 

using PrefetchingLSU =
  ext::intel::lsu<ext::intel::prefetch<true>,
                  ext::intel::statically_coalesce<false>>;

int X = PrefetchingLSU::load(input_ptr);

Cache

The cache control helps the Intel® oneAPI DPC++/C++ Compiler turn on or off caching behavior and set the size of the cache. This LSU modifier can be useful for parallel_for kernels. The cache control can be combined with other attributes such as burst_coalesce. For more details about this LSU modifier, refer to Cached.

The following is an example of cache LSU control: 

using CachingLSU =
  ext::intel::lsu<ext::intel::burst_coalesce<true>,
		                ext::intel::cache<1024>,
		                ext::intel::statically_coalesce<false>>;

int X = CachingLSU::load(input_ptr);

Pipeline

The pipeline control helps the Intel® oneAPI DPC++/C++ Compiler infer the LSU style of pipeline. It can be combined with other attributes such as static coalesce. For more details about this LSU type, refer to Pipelined Load-Store Units.

For example: 

using PipelinedLSU = ext::intel::lsu<>;

PipelinedLSU::store(output_ptr,X);
Parent topic: Load-Store Units
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