Developer Guide
Visible to Intel only — GUID: GUID-C8C9C0E7-7289-495B-B8D3-29ABA5D720AE
Visible to Intel only — GUID: GUID-C8C9C0E7-7289-495B-B8D3-29ABA5D720AE
Intel oneAPI DPC++/C++ Compiler Handbook for FPGAs Overview
The Intel® oneAPI DPC++/C++ Compiler Handbook for FPGAs provides guidance on leveraging the functionalities of data parallel C++ (DPC++) and the SYCL* cross-platform abstraction layer to optimize your design.
A good way to learn about SYCL* programming for Altera® FPGA devices is to work through the oneAPI samples for FPGAs available on GitHub: oneAPI Samples for FPGA.
For more information, about SYCL and programming in DPC++, refer to the following publications:
- SYCL* 2020 Specification by the Khronos* Group. (https://registry.khronos.org/SYCL/specs/sycl-2020/html/sycl-2020.html)
The SYCL* specification provides detailed descriptions of SYCL concepts and application programming interfaces (APIs).
- Data Parallel C++: Programming Accelerated Systems Using C++ and SYCL* (https://link.springer.com/book/10.1007/978-1-4842-9691-2)
This free book teaches you how to accelerate C++ programs using data parallel programming that targets various device types, including FPGA devices.
Intel® oneAPI DPC++/C++ Compiler Handbook for FPGAs Organization
This guide is organized into the following parts:
- Introduction To FPGA Design Concepts
A description of FPGA hardware concepts and how the Intel® oneAPI DPC++/C++ Compiler converts your code to an FPGA application.
- Intel® oneAPI FPGA development flow:
- Intel oneAPI FPGA Development provides an overview of the FPGA development flow.
- Defining a Kernel for FPGAs provides coding guidelines for your kernel
- Optimizing Your Kernel provides an overview of methods to optimize your kernel performance and the parts of your kernel code that you can examine to improve performance.
- Optimizing Your Host Application provides techniques to optimize the host application part of your multiarchitecture binary. This chapter does not apply for developing RTL IP cores.
- Analyzing Your Design provides information about tools and techniques that you can use analyze your kernel design without running the kernel on hardware. Use these tools and techniques to determine what parts of your kernel you can optimize or adjust before your compile your kernel for FPGA hardware.
- Debugging and Verifying Your Design provides information about tools and techniques that you can use to verify the functional correctness of your kernel.
- Integrating Your RTL IP Core Into a System provides information about how to integrate an RTL IP core generated by the Intel® oneAPI DPC++/C++ Compiler into a larger FPGA design.
- Optimization areas:
- Libraries covers using libraries in your kernel and generating libraries from your kernel.
- Additional considerations when developing your kernel:
- Reference material:
- FPGA Optimization Flags, Attributes, Pragmas, and Extensions:
Describes a list of compiler optimization flags, attributes, pragma, and extensions that allow you to customize the kernel compilation process.
- Quick Reference:
A cheat sheet of all FPGA-specific attributes, pragmas, and variables.
- FPGA Optimization Flags, Attributes, Pragmas, and Extensions: