Developer Guide

Intel oneAPI FPGA Handbook

Download PDF
ID 785441
Date 2/07/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
Intel® oneAPI FPGA Handbook Introduction To FPGA Design Concepts Intel oneAPI FPGA Development Defining a Kernel for FPGAs Debugging and Verifying Your Design Analyzing Your Design Optimizing Your Kernel Optimizing Your Host Application Integrating Your RTL IP Core Into a System RTL IP Core Kernel Interfaces Loops Pipes Data Types and Arithmetic Operations Parallelism Memories and Memory Operations Libraries Additional FPGA Acceleration Flow Considerations Additional SYCL* HLS Flow Considerations FPGA Optimization Flags, Attributes, Pragmas, and Extensions Quick Reference Additional Information Document Revision History for the Intel oneAPI FPGA Handbook Notices and Disclaimers
Introduction To FPGA Design Concepts x
FPGA Architecture Overview Concepts of FPGA Hardware Design How Source Code Becomes a Custom Hardware Datapath
How Source Code Becomes a Custom Hardware Datapath x
Mapping Source Code Instructions to Hardware Scheduling Mapping Parallelism Models to FPGA Hardware Memory Types
Intel oneAPI FPGA Development x
FPGA Flow Terminology Intel oneAPI FPGA Development Flow Types of SYCL* FPGA Compilation FPGA Compilation Flags FPGA Workflows in IDEs
Types of SYCL* FPGA Compilation x
Separating Device and Host Code Compilation
Defining a Kernel for FPGAs x
Suggested Kernel Coding Styles Single Work-Item Kernels
Single Work-Item Kernels x
Single Work-item Kernel Design Guidelines Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels
Single-Cycle Floating-Point Accumulator for Single Work-Item Kernels x
Strategies for Inferring the Accumulator
Debugging and Verifying Your Design x
Device Selectors for FPGA printf Command Restrictions Emulate and Debug Your Design Evaluate Your Kernel Through Simulation
Emulate and Debug Your Design x
Emulator Environment Variables Compile and Emulate Your Design Limitations of the Emulator Troubleshooting Discrepancies in Hardware and Emulator Results Emulator Known Issues
Evaluate Your Kernel Through Simulation x
Debug During Verification Simulation Prerequisites Installing the Questa*-Intel FPGA Edition Software Set Up the Simulation Environment Compile a Kernel for Simulation Simulate Your Kernel Viewing Simulation Waveforms Troubleshooting Simulator Issues
Analyzing Your Design x
Analyze the FPGA Early Image Analyze the FPGA Image Review the FPGA Optimization Report Quartus (Static) Summary Intel® FPGA Dynamic Profiler for DPC++ System-level Profiling Using the Intercept Layer for OpenCL™ Applications
Review the FPGA Optimization Report x
Loop Analysis Bottlenecks Viewer Area Estimates System Viewer Kernel Memory Viewer Schedule Viewer Access HLD FPGA Reports in JSON Format
Quartus (Static) Summary x
Timing Failures
Intel® FPGA Dynamic Profiler for DPC++ x
Measure Kernel Performance Instrument the Kernel Pipeline with Performance Counters (-Xsprofile) Obtain Profiling Data During Run Time Reduce Area Resource Use While Profiling Profiler Analyses of Example SYCL* Design Scenarios Limitations
Obtain Profiling Data During Run Time x
Invoke the Profiler Runtime Wrapper to Obtain Profiling Data Use Intel® VTune™ Profiler
Use Intel® VTune™ Profiler x
Interpret Performance Counter Data
System-level Profiling Using the Intercept Layer for OpenCL™ Applications x
Set Up the Intercept Layer for OpenCL™ Applications
Optimizing Your Host Application x
Throughput Resource Use Multi-Threaded Host Application Utilizing Hardware Kernel Invocation Queue Double Buffering Host Utilizing Kernel Invocation Queue N-Way Buffering to Overlap Kernel Execution Prepinning Memory Simple Host-Device Streaming Buffered Host-Device Streaming
Double Buffering Host Utilizing Kernel Invocation Queue x
Applying Double-Buffering Using the Intercept Layer for OpenCL™ Applications
Integrating Your RTL IP Core Into a System x
Synthesize Your RTL IP Core with Intel Quartus Prime Software Add RTL IP Component into a Platform Designer System Add an RTL IP Component into an Intel® Quartus® Prime Project Encrypt RTL IP Components for Distribution
RTL IP Core Kernel Interfaces x
Kernel Argument Interfaces Memory-Mapped (MM) Agent Kernel Invocation Interface Ready/Valid Handshaking Kernel Invocation Interface Memory-Mapped Host Interfaces
Memory-Mapped Host Interfaces x
Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the annotated_arg Class Memory-Mapped Host Interfaces Using Accessors (Deprecated) Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the mmhost Macro
Memory-Mapped Host Interfaces Using Unified Shared Memory Pointers and the annotated_arg Class x
Buffer Locations in Memory-Mapped Host Interfaces The annotated_arg Template Class
Loops x
Refactor the Loop-Carried Data Dependency Relax Loop-Carried Dependency Transfer Loop-Carried Dependency to Local Memory Minimize the Memory Dependencies for Loop Pipelining Unroll Loops Fuse Loops to Reduce Overhead and Improve Performance Optimize Loops With Loop Speculation Remove Loop Bottlenecks Improve fMAX/II with Shannonization Optimize Inner Loop Throughput Improve Loop Performance by Caching Data in On-Chip Memory
Pipes x
Host Pipes Pipes Extension Emulate Applications with a Pipe That Reads or Writes to an I/O Pipe
Host Pipes x
Host Pipe Declaration Host Pipe API Host Pipes RTL Interfaces
Pipes Extension x
Key Properties of a Pipe Accessing Pipes The pipe Class and its Use I/O Pipes Characteristics of Pipes Restrictions of Pipes Guidelines for Designing Pipes The atomic_fence Function and Pipes
Data Types and Arithmetic Operations x
Optimize Floating-point Operation Avoid Expensive Functions Variable-Precision Data Type Support
Variable-Precision Data Type Support x
Advantages and Limitations of Variable Precision Data Types Declare and Use the AC Data Types
Declare and Use the AC Data Types x
Declare the ac_int Data Type Declare the ac_fixed Data Type Declare the ac_complex Data Type Declare the ap_float Data Type
Declare the ap_float Data Type x
Conversion Rules for the ap_float Data Type Operations with Explicit Precision Controls Comparison Operators Additional ap_float Functions Additional Data Types Provided by the ap_float.hpp Header File Quality of Results and the ap_float Data Type
Parallelism x
Pipelined Kernels NDRange Kernels Asynchronous Parallelism Within Kernels (task_sequence)
Pipelined Kernels x
Stable Arguments
Asynchronous Parallelism Within Kernels (task_sequence) x
Task Functions task_sequence Use Cases
Memories and Memory Operations x
The device_global Extension (Beta) Memory Accesses Kernel Variable Accesses
Memory Accesses x
Load-Store Units Global Memory Accesses Optimization Perform Kernel Computations Using Local or Private Memory Local and Private Memory Accesses Optimization Annotating Unified Shared Memory Pointers Zero-Copy Memory Access Additional Recommendations
Load-Store Units x
Load-Store Unit Styles Load-Store Unit Modifiers Load-Store Unit Controls
Global Memory Accesses Optimization x
Global Memory Bandwidth Use Calculation Manual Partition of Global Memory Partitioning Buffers Across Different Memory Types (Heterogeneous Memory) Partitioning Buffers Across Memory Channels of the Same Memory Type Ignoring Dependencies Between Accessor Arguments Contiguous Memory Accesses Static Memory Coalescing
Libraries x
Use SYCL Shared Library With Third-Party Applications Use of RTL Libraries for FPGA Object Manifest File Syntax of an RTL Library Restrictions and Limitations in RTL Support Intel® Stratix® 10 and Intel Agilex® 7 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Libraries Stall-Free RTL
Additional FPGA Acceleration Flow Considerations x
FPGA-CPU Interaction FPGA BSPs and Boards Targeting Multiple Homogeneous FPGA Devices Targeting Multiple Platforms Split Kernel into Multiple FPGA Images (Linux only)
FPGA BSPs and Boards x
FPGA Board Initialization Obtain FPGA Hardware Image Information Extracting the FPGA Hardware Configuration (.aocx) File from a Multiarchitecture Binary File
Additional SYCL* HLS Flow Considerations x
IP Component Reset Behavior
FPGA Optimization Flags, Attributes, Pragmas, and Extensions x
Optimization Flags Optimization Targets Kernel Variables Kernel Attributes Memory Attributes Loop Directives Floating-Point Pragmas Latency Controls (Beta)
Optimization Flags x
Specify Schedule FMAX Target for Kernels (-Xsclock=<clock target>) Create a 2xclock Interface (-Xsuse-2xclock) Disable Burst-Interleaving of Global Memory (-Xsno-interleaving=<global_memory_name>) Force Ring Interconnect for Global Memory (-Xsglobal-ring) Force a Single Store Ring to Reduce Area (-Xsforce-single-store-ring) Force Fewer Read Data Reorder Units to Reduce Area (-Xsnum-reorder) Disable Hardware Kernel Invocation Queue (-Xsno-hardware-kernel-invocation-queue) Modify the Handshaking Protocol Between Clusters (-Xshyper-optimized-handshaking) Disable Automatic Fusion of Loops (-Xsdisable-auto-loop-fusion) Fuse Adjacent Loops With Unequal Trip Counts (-Xsenable-unequal-tc-fusion) Pipeline Loops in Non-task Kernels (-Xsauto-pipeline) Control Semantics of Floating-Point Operations (-fp-model=<value>) Modify the Rounding Mode of Floating-point Operations (-Xsrounding=<rounding_type>) Global Control of Exit FIFO Latency of Stall-free Clusters (-Xssfc-exit-fifo-type=<value>) Enable the Read-Only Cache for Read-Only Accessors (-Xsread-only-cache-size=<N>) Control Hardware Implementation of the Supported Data Types and Math Operations (-Xsdsp-mode=<option>) Generate Register Map Wrapper (-Xsregister-map-wrapper-type)
Optimization Targets x
Minimum Latency Flow Balanced Throughput-Area Trade-Offs Flow
Kernel Attributes x
Specify Schedule FMAX Target for Kernels Specify a Workgroup Size Specify Number of SIMD Work Items Omit Hardware that Generates and Dispatches Kernel IDs Omit Hardware to Support the no_global_work_offset Attribute in parallel_for Kernels Reduce Kernel Area and Latency
Loop Directives x
disable_loop_pipelining Attribute initiation_interval Attribute ivdep Attribute loop_coalesce Attribute max_concurrency Attribute max_interleaving Attribute speculated_iterations Attribute unroll Pragma Loop Fuse Functions and nofusion Attribute max_reinvocation_delay Attribute (Beta)
Quick Reference x
Algorithmic C Data Types Floating Point Pragmas FPGA Accessor Properties FPGA Extensions FPGA Kernel Attributes FPGA Local Memory Function Latency Control Properties (Beta) FPGA LSU Controls FPGA Loop Directives FPGA Memory Attributes FPGA Optimization Flags Pipe API
Intel® oneAPI FPGA Handbook
Introduction To FPGA Design Concepts
Intel oneAPI FPGA Development
Defining a Kernel for FPGAs
Debugging and Verifying Your Design
Analyzing Your Design
Optimizing Your Kernel
Optimizing Your Host Application
Integrating Your RTL IP Core Into a System
RTL IP Core Kernel Interfaces
Loops
Pipes
Data Types and Arithmetic Operations
Parallelism
Memories and Memory Operations
Libraries
Additional FPGA Acceleration Flow Considerations
Additional SYCL* HLS Flow Considerations
FPGA Optimization Flags, Attributes, Pragmas, and Extensions
Quick Reference
Additional Information
Document Revision History for the Intel oneAPI FPGA Handbook
Notices and Disclaimers

Buffered Host-Device Streaming

In this topic, you learn how to optimize a full system design that streams data from the host to the device and back to the host and create heterogeneous designs that can achieve high throughput. The techniques described in this topic are not specific to a CPU-FPGA system, and you can apply them to GPUs, multi-core CPUs, and other processing units as well.

TIP:
If your BSP supports host pipes, use them instead of buffered host-device streaming. For information about host pipes, refer to Host Pipes.

IMPORTANT:

Prior to learning about buffered host-device streaming concept, you must review the following concepts:

To understand the concept of buffered host-device streaming, consider an example design where a Producer (running on the CPU) produces data into USM host allocations, a Kernel (running on the FPGA) processes this data and produces output into host allocations, and a Consumer (running on the CPU) consumes the data. Data is shared between the host and FPGA device via host pointers (pointers to USM host allocations).

Example Design with a Producer, Kernel, and Consumer

In heterogeneous systems, it is important to understand how different compute architectures are connected (that is, how data is transferred from one to another) to better reason about and address performance bottlenecks in the system. The following figure is a slightly more detailed illustration of the processing pipeline in the example design, which shows the data flow between the Producer, Kernel, and Consumer. It illustrates that the Producer and Consumer operations both execute on the CPU and communicate with the FPGA kernel over a PCIe link (PCIe Gen3 x16).

Detailed Illustration of the Processing Pipeline

Roofline Analysis

When designing for throughput, you must first estimate the maximum throughput the system is capable of. This back-of-the-envelop calculation is called roofline analysis. To calculate the maximum achievable throughput of the Producer-Kernel-Consumer design shown in Figure 2, assume that the Producer and Consumer have infinite bandwidth (that is, they can produce or consume data at an infinite rate, respectively). Then, the bottleneck in the system is the FPGA kernel. Assume that the kernel has an fMAX of 400MHz and processes 64 bytes per cycle. The following is kernel's maximum steady-state throughput:

400 MHz * 64 bytes/cycle = 25.6 GB/s ~= 26 GB/s.

In reality, the rate of data transfer to and from the kernel depends on the bandwidth of the PCIe link. In Figure 2, you can observe that this depends on the bandwidth of the PCIe link. It has been experimentally measured that the PCIe Gen3 x16 link has a total bandwidth of ~22 GB/s (11 GB/s bidirectional). This means that, while the kernel can process data at 26 GB/s, you can only send data to it and receive from it at a rate of 11 GB/s. The system bottleneck is the PCIe link between the CPU and FPGA. It is common for the bottleneck in a heterogeneous system to be the inter-device link, rather than any single device.

In this analysis so far, you assumed that the Producer and Consumer had infinite bandwidth. You can now perform a roofline analysis on the entire system by assuming a finite bandwidth for the Producer and Consumer. For the entire Producer-Kernel-Consumer design, the maximum possible throughput is the minimum of the Producer, Kernel, and Consumer throughput, and the bandwidth of the link (in this case, PCIe) connecting the CPU and FPGA (a chain is only as strong as the weakest link).

Optimizing the Design for Throughput

A naive approach to this design is for the Producer, Kernel, and Consumer to run sequentially that is depicted by the following timing diagram. This naive approach underperforms because operations, which could run in parallel, are run sequentially. For example, in the following figure, the Producer could be producing the second set of data, while the Consumer is consuming the first set of data:

Timing Diagram

To improve the performance, you can create a separate CPU thread (called the Producer thread) that produces all of the data for the Kernel to process, and consumes later as shown in the following figure. This allows the Producer and Consumer to run in parallel (that is, the Producer thread produces the next set of data, while the Consumer consumes the current data).

Timing Diagram with Producer and Consumer Running in Parallel

This approach improves the design's throughput, but does require more complicated thread synchronization logic to synchronize between the Producer thread and the main thread that is launching kernels and consuming its output.

Observe that in the Figure 4, the Producer and Consumer are running simultaneously (in separate threads). You must consider the fact that both of these processes are running on the CPU in parallel, which affects their individual throughput capabilities. For example, running these processes in parallel can result in saturating the CPU's memory bandwidth, and therefore lower the overall throughput for the Producer and Consumer processes even if the threads run on different CPU cores.

By putting the Producer into its own thread, you can improve performance by producing and consuming data simultaneously. However, it is ideal if the Producer can produce the next set of data while the kernel is processing the current data. This allows the next kernel to launch as soon as the current kernel finishes, instead of waiting for the Producer to finish, as shown in Figure 4. Unfortunately, you cannot produce data into the buffer that the kernel is currently processing, since it is still in use by the kernel. To address this, use multiple buffers (that is, N-Way buffering) of the input and output buffers, which results in a timing diagram, as shown in the following:

Timing Diagram With Multiple Buffers

The subscript number on the Producer and Consumer (for example, Producer0 and Consumer0) represents the buffer index they are processing. The Figure 5 illustrates the case where you use two sets of buffers (double-buffering). Observe that in Figure 5, the Producer produces into buffer 1 (Producer1) while the kernel is processing the data from buffer 0. Thus, by the time the kernel finishes processing buffer 0, it can start processing buffer 1 right away, so long as the Producer has finished producing the next buffer of data.

In the steady-state for Figure 5, the throughput of the design is bottlenecked by the throughput of the slowest stage (the Producer, Kernel, or Consumer), which matches the Roofline Analysis you did earlier. For example, the Figure 6 shows an example timeline where the Kernel is the throughput bottleneck. The Figure 7 shows an example timeline where the Producer (or Consumer) is the bottleneck.

Timing Diagram With Kernel as the Throughput Bottleneck

Timing Diagram With Producer/Consumer as the Throughput Bottleneck

Streaming API

In the Buffered Host-Device Streaming example on GitHub, the techniques described in the previous section are implemented in two ways. The design is implemented directly using SYCL USM host allocations and C++ multithreading, and the kernel queue is managed intelligently. The code achieves high performance, but it might be difficult to understand and extend it to different designs. To address this, a convenient and performant API wrapper (HostStreamer.hpp) is created. The same design is implemented in streaming_with_api.hpp with similar performance and significantly less code that is much easier to understand.

IMPORTANT:

While the code that uses the HostStreamer API achieves similar performance to a direct implementation, it uses extra FPGA resources. The direct implementation has a single kernel (Kernel) that does all the processing. Using the API creates a Producer and Consumer kernel that access host allocations and produce/consume data to/from the processing kernel (APIKernel in streaming_with_api.hpp). These extra kernels (that are transparent) are the mechanism by which the API abstracts the production/consumption of data, but come at the cost of extra FPGA resources. However, when compiled for the Intel FPGA PAC D5005, these extra kernels result in less than 1% increase in FPGA resource utilization. Therefore, given the programming convenience they provide, the tradeoff is often worth it.

NOTE:

For additional information, refer to the FPGA tutorial sample "Buffered Host-Device Streaming" listed in the Intel® oneAPI Samples Browser on Linux* or Windows*, or access the code sample on GitHub.

Parent topic: Optimizing Your Host Application
Level Two Title