Visible to Intel only — GUID: GUID-4BC10447-ED1A-45CD-827E-8670B6F3B0EA
Visible to Intel only — GUID: GUID-4BC10447-ED1A-45CD-827E-8670B6F3B0EA
Intel® Stratix® 10 and Intel Agilex® 7 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Libraries
When creating an RTL library for Intel® Stratix® 10 SYCL and Intel Agilex® 7 designs, ensure that the library satisfies specific logic reset requirements.
Reset Requirements for Stall-Free RTL Libraries
A stall-free RTL library is a fixed-latency library for which the Intel® oneAPI DPC++/C++ Compiler can optimize away stall logic. It accepts valid data, and does not have a ready_in signal at the end.
When creating a stall-free RTL library for an Intel® Stratix® 10 design, use synchronous clear signals only.
After deassertion of the reset signal to the stall-free RTL library, the library must be operational within 15 clock cycles. If the reset signal is pipelined within the library, this requirement limits the reset pipelining to no more than 15 stages.
Reset Requirements for Stallable RTL Libraries
A stallable RTL library has a variable latency, and it relies on backpressured input and output interfaces to function correctly.
When creating a stallable RTL library for an Intel® Stratix® 10 and Intel Agilex® 7 designs, use synchronous clear signals only.
After assertion of the reset signal to the stallable RTL library, the library must deassert its oready and ovalid interface signals within 40 clock cycles.
After deassertion of the reset signal to the stallable RTL library, the library must be fully operational within 40 clock cycles. The library signals its readiness by asserting the oready interface signal.