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1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
2.1. Creating an EMIF Project
2.2. Generating and Configuring the EMIF IP
2.3. Configuring DQ Pin Swizzling
2.4. Generating the Synthesizable EMIF Design Example
2.5. Generating the EMIF Design Example for Simulation
2.6. Pin Placement for Agilex™ 5 EMIF IP
2.7. Compiling the Agilex™ 5 EMIF Design Example
2.8. Using the Design Example with the Test Engine IP
2.9. Generating the EMIF Design Example with the Performance Monitor
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface
2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width
2.3.3. Combining Pin and Byte Swizzling
2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface
2.3.5. Example: Byte Swizzling for Lockstep Configuration
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2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
An automated design example flow is available for Agilex™ 5 external memory interfaces.
The Generate Example Designs button on the Example Designs tab allows you to specify and generate the synthesis and simulation design example file sets which you can use to validate your EMIF IP.
You can generate a design example that matches the Altera FPGA development kit, or for any EMIF IP that you generate. You can use the design example to assist your evaluation, or as a starting point for your own system.
Figure 1. General Design Example Workflows
Section Content
Creating an EMIF Project
Generating and Configuring the EMIF IP
Configuring DQ Pin Swizzling
Generating the Synthesizable EMIF Design Example
Generating the EMIF Design Example for Simulation
Pin Placement for Agilex 5 EMIF IP
Compiling the Agilex 5 EMIF Design Example
Using the Design Example with the Test Engine IP
Generating the EMIF Design Example with the Performance Monitor