External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Using the Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.1. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4
2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4 x
2.1.1.3.3.1. Guidelines for Selecting the LPDDR4 Component
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface 2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

3.1. Synthesis Design Example

The synthesis design example contains the major blocks described below.
  • A traffic generator is a synthesizable AXI4 driver that implements a hard-coded pattern and monitors the data read from the memory to ensure that it matches the written data, and asserts a failure otherwise. You can select different traffic generator programs when generating the example design. Each program performs the following transactions:
    • Single write and read (with AxLEN=axlen_a 1 ) 2
    • Single write and read (with AxLEN=axlen_b 1 ) 2
    • Sequential address 3 block of m 4 writes and m 4 reads (with AxLEN=axlen_a 1 )
    • Sequential address 3 block of m 4 writes and m 4 reads (with AxLEN=axlen_b 1 )
    • Random address 5 block of m 4 writes and m 4 reads (with AxLEN=axlen_a 1 )
    1 The axlen_a and axlen_b values depend on the memory technology.
    2 Repeated for 3 loops in the traffic generator program = Short.
    3 Sequential Address pattern starts at address=0, and increments by (AXI_DATA_WIDTH/8)*(AxLEN+1) on each transaction.
    4 The m value depends on the traffic generator program.
    5 Random address pattern starts at address=0, and uses pseudo-random addresses.
    Table 14.  axlen_a and axlen_b for Different memory Technologies
    Technology axlen_a axlen_b Notes
    DDR4 0 0  
    DDR5 1 0 axlen_b=0 results in Read-Modify-Write or data-masking on the memory side.
    LPDDR4 3 3  
    LPDDR5 1 1  
    Table 15.   m value in Different Traffic Generator programs
    Traffic Generator Program m
    Short 128
    Medium 512
    Long 4096
  • An instance of the memory interface, which includes:
    • A memory controller which implements all the memory commands and protocol-level requirements.
    • The PHY, which serves as an interface between the memory controller and external memory devices to perform read and write operations.
Figure 35. Synthesis Design Example Sync Fabric Mode

Synthesis Example Design

Figure 36. Synthesis Design Example Async Fabric Mode

You must add the following assignment to the .qsf file to allow for less-restricted placement of the user PLL: 

set_instance_assignment –name PLL_REFCLK_INPUT_TYPE NOT_BALANCED -to user_pll|altera_iopll_inst

If a user PLL shares an I/O bank with EMIF, you may additionally need to specify an operating voltage I/O standard. The voltage of the pin depends on the operating voltage of the EMIF occupying that bank, which, in turn, depends on the memory protocol, as follows:

  • DDR4 = 1.2V
  • DDR5 = 1.1V
  • LPDDR4 = 1.1V
  • LPDDR5 = 1.05V

For example, for a PLL whose reference clock is in the same bank as an LPDDR4 EMIF, the assignment show look like this:

set_instance_assignment -name IO_STANDARD "1.1V True Differential Signaling" -to "ref_clk_usr_pll"
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