External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 817394
Date 7/08/2024
Public
Document Table of Contents

2.1.1.3.3.1. Guidelines for Selecting the LPDDR4 Component

For LPDDR4 discrete components, the Agilex™ 5 LPDDR4 IP supports the following:

  • 1 die per component with 1 rank.
  • 2 dies per component with 1 rank.
  • 2 dies per component with 2 ranks.
  • 4 dies per component with 2 ranks.