External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Using the Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.1. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4
2.1.1.3.3. Generating a Custom Memory Preset File for LPDDR4 x
2.1.1.3.3.1. Guidelines for Selecting the LPDDR4 Component
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface 2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type

For DDR4 discreet components, the Agilex™ 5 DDR4 IP supports the following package types:
  • 1 die per component
  • 2 dies per component with 1 rank
  • 2 dies per component with 2 ranks

Because the Agilex™ 5 DDR4 IP does not support x4 discrete memory component/die, you can use only x16 DQ width components for a 2 Dies Per Component, 1 Rank package. In this combination, two x8 dies are combined in a single package to make one x16 component as shown below.

Figure 10. Functional Block Diagram for 2 Dies Per Component, 1 Rank Package
Note:

You must set the Device DQ width to 16 when selecting 2 Dies per Component, 1 Rank. Otherwise, the following error message appears: Discrete memory device consists of x4 die is not supported by the current version of Platform Designer.

For a 2 Dies Per Component, 2 Rank package, the DQ Width of the component is the same as the base die; it is essentially two ranks of the base die, as illustrated below.

Figure 11. Functional Block Diagram for 2 Dies Per Component, 2 Rank Package
Note:

You must set the Memory Ranks to 2 when parameterizing an EMIF IP using a custom preset file generated with a 2 Dies Per Component, 2 Rank package. Otherwise, the following error message appears: The number of ranks in each memory component (2) cannot divide the total number of ranks in the interface (1).

Figure 12. Setting Memory Ranks to 2 in the EMIF IP
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